john.zhang
Newbie level 5
I am designing an LNA for 30 to 45 GHz using SOI CMOS. I am using cadence virtuoso to simulate it, while my passive devices are EM simulated on ADS. All the guides I see online, usually start their SP analysis at 1 GHz, and so I also do that, and everything is fine.
However, I recently tried to do an SP analysis from 0 Hz, with a step size of 0.1G, and at cadence gives a warning of arithmetic exception, and at 0Hz it returns a kfactor of 0 as well as an S21 magnitude of 0, which is why I guess the kfactor is 0 because an S21 of 0 would yield an indeterminate kfactor result.
Is this a cause for worry or is this just a case of cadence not being able to compute it properly?
I do have a DC blocking cap in my LNA input, which could block DC to a few hundred megahertz, so is it correct in thinking that any instability up to a few hundred megahertz should not matter?
Thanks!
However, I recently tried to do an SP analysis from 0 Hz, with a step size of 0.1G, and at cadence gives a warning of arithmetic exception, and at 0Hz it returns a kfactor of 0 as well as an S21 magnitude of 0, which is why I guess the kfactor is 0 because an S21 of 0 would yield an indeterminate kfactor result.
Is this a cause for worry or is this just a case of cadence not being able to compute it properly?
I do have a DC blocking cap in my LNA input, which could block DC to a few hundred megahertz, so is it correct in thinking that any instability up to a few hundred megahertz should not matter?
Thanks!