LNA for Neural Recording Layout Design

[didid]

Hello everyone.
I am having difficulties in post-simulation after extracting PEX data.

The picture above is my schematic for neural recording.
I extracted all the PEX data of each sub-block circuit and I made the schematic into one symbol to do post-simulation.

As you can see in those 2 pictures, the left one is simulated with PEX data of each sub-block, while the right one is for the entire symbol.

The results of the two simulations were too different.

The transient output of the LNA and the transfer function of the schematic are different.
The pink graph on the left and the green graph on the right are the results of the sub-block PEX simulation.
and the purple graph on the left and the blue graph on the right are the results of the whole symbol PEX simulation.

Do you know why this is happening?
The devices used in the schematic besides the sub-block are capacitors. In my opinion, there is a problem when extracting the PEX data of those capacitors.

How can I solve this problem? Should I make layout routing again?
I'd love to hear your opinion.

 

[sidun.av]

Hi @didid

As I understand, you have an LNA that works as expected when you simulate it with extraction on a sub-block level, but it fails when you simulate it on a top level. Is that correct?

There are a few more questions to understand your issue better:

• Is there any difference from schematic vs. sub-block extraction sim results? It also worth verifying (by inspecting the simulation log) that cells are actually replaced by calibre view;
• What technology do you use? If this is TSMC 28nm or lower, you have to use HCELLs for capacitors during extraction to get a correct result.
• Did you check the power consumption of your extracted sim? Is there any significant difference from schematic sim?

Once these questions are answered, you can proceed to a layout inspection:
- check that all important nodes have proper voltages/currents;
- check the sensitive (weak) nodes for excessive parasitics in Calibre PEX;
Also, it would be quite useful to have a look on your LNA-level layout (please, do not invert the colours)...

I can recommend the following debugging procedure:

1. Keep your input stimulus simple, i.e. sinusoidal;
2. Keep you simulation as short as possible (to reduce simulation time);
3. Perform a schematic sim and inspect the behavior of the sensitive nodes for voltages/currents;
4. Perform the same simulation with your extraction and start expecting the nodes while moving from input to the output;
5. Spot the difference, then find the reason in layout;
6. Improve your layout, re-extract and re-simulate your circuit.

Hopefully, that helps.