Linearity of S&H circuit with incomplete settling

[mixed_signals]

Hello All,

What I know from my previous study that we should choose the time constant of the track & hold circuit with respect to the target resolution and the available tracking time such that the error is <= LSB/2. For higher target resolutions and smaller tracking times --> this time constant gets very small which means we need ultra high bandwidth track & hold buffers.

Larger time constant of the track & hold buffer will cause incomplete settling in the available time window and hence an error larger than the target resolution.
so my question: Does this incomplete settling (error > LSB/2) cause a linearity degradation?

Thank you in advance!

 

[nitishn5]

Yes.
Since the settling error is a function of the input. It will be a different amount for different inputs and not like a constant offset.

 

[FvM]

Surely not an offset. Deviation proportional to signal delta would be the expected linear error function. However due to varying switch resistance and driver amplifier output stage non-linearity, the error becomes non-proportiinal and thus non-linear.

 

[KlausST]

Hi,

offset may be caused by charge injection of the switches.

Klaus

 

[mixed_signals]

Yes.
Since the settling error is a function of the input. It will be a different amount for different inputs and not like a constant offset.

I think that settling error will be a fixed percentage of each input. For example, if the available tracking time window is equal to just one time constant then the input will settle to about 63% every cycle, won't it?

Second thing, I am talking here about an ideal linear buffer, how does incomplete settling of "ideal linear" buffer cause linearity degradation?

 

[mixed_signals]

Surely not an offset. Deviation proportional to signal delta would be the expected linear error function. However due to varying switch resistance and driver amplifier output stage non-linearity, the error becomes non-proportiinal and thus non-linear.

Yes, I agree that non-linearity of the switch and buffer will cause distortion in the output.

If we assume an ideal switch and buffer "ideal S/H circuit" then there is no linearity degradation even if there is incomplete settling right?

--- Updated Jun 21, 2024 ---

Hi,

offset may be caused by charge injection of the switches.

Klaus

Yes, I agree that charge injection will cause errors.

But here in my question, I want to investigate the effect of "only" incomplete settling of the input on the linearity assuming that all other errors are zero.

 

[KlausST]

Hi,

I want to investigate the effect of "only" incomplete settling

if you idealize it to a clean RC:
then you may calculate tau ... and according this you may cause the settling error vs acquisition time.
Even in the idealized view I expect some issues. (1st order low pass)
* what is the previous charge state of the holding capacitor?
- I´ve seen: V_ref, 0V, last holding value, last holding value of a different channel...
And in a more realistic view:
* non linearity of switch resistance
* ringing caused by stray inductance (there may be overshot, and one microsecond later undershot..)
* ringing caused by the driving OPAMP
* moving input signal with varying dV/dt
* production tolerances
* maybe more

Klaus

Btw: nowadays we have good simualtion software. Why don´t you simulate the different conditions?

 

[mixed_signals]

Hi,

if you idealize it to a clean RC:
then you may calculate tau ... and according this you may cause the settling error vs acquisition time.
Even in the idealized view I expect some issues. (1st order low pass)
* what is the previous charge state of the holding capacitor?
- I´ve seen: V_ref, 0V, last holding value, last holding value of a different channel...
And in a more realistic view:
* non linearity of switch resistance
* ringing caused by stray inductance (there may be overshot, and one microsecond later undershot..)
* ringing caused by the driving OPAMP
* moving input signal with varying dV/dt
* production tolerances
* maybe more

Klaus

Btw: nowadays we have good simualtion software. Why don´t you simulate the different conditions?

Thank you for your response.

Actually, I already have simulated an ideal track and hold circuit (ideal buffer is modeled as a linear VCCS with finite output resistance and capacitance) + ideal switch + ideal analoglib capacitor. I chose the time constant of the ideal buffer to be close to the available tracking time to model the incomplete settling. I assumed that the capacitor hold the previous input sample (no reset).

According to the above condition, I would have expected that ENOB of the output signal (S/H signal) to match the ENOB of the input sinusoidal input because all included circuit elements are ideal and linear so it seems that incomplete settling of every input sample is the cause of this linearity degradation.

For reference, ENOB of an ideal sinusoidal input was about 44 bits
After S/H, ENOB becomes about 14 bits (conservative settings)


As I tighten reltol of the simulator, I get better ENOB for the S/H signal. Also, when I changed max_step to 1 ps, I got about 22 bits for the output (still lower than the input).

According to this large variation of ENOB with the accuracy settings, I do not have full confidence in my conclusion that incomplete settling deteriorates the linearity.

 

[dick_freebird]

If you consider this to be a T/H slew rate problem then it's worst at full scale input jump in a single sample period.

Does your input waveform ever do that and if it does, is that "valued signal" or abnormal, "fuggedaboudit"?

Input sample settling time should be better the smaller the code transition. Large signal slew time concatenated with small signal settling time

Can you go lower on hold cap and cut slew time? Settling could go either way. Droop / hold time must not be a concern if you're up against settling time for accuracy, check the trades?

 

[mixed_signals]

If you consider this to be a T/H slew rate problem then it's worst at full scale input jump in a single sample period.

Does your input waveform ever do that and if it does, is that "valued signal" or abnormal, "fuggedaboudit"?

Input sample settling time should be better the smaller the code transition. Large signal slew time concatenated with small signal settling time

Can you go lower on hold cap and cut slew time? Settling could go either way. Droop / hold time must not be a concern if you're up against settling time for accuracy, check the trades?

Thank you for your response.

Actually, I am afraid that I did not get exactly what you mean or what you are trying to convey with respect to my inquiry about the relationship between incomplete settling (tracking error) and the linearity of the S/H circuit. Kindly, elaborate more.

--- Updated Jun 22, 2024 ---

@

Hi,

if you idealize it to a clean RC:
then you may calculate tau ... and according this you may cause the settling error vs acquisition time.
Even in the idealized view I expect some issues. (1st order low pass)
* what is the previous charge state of the holding capacitor?
- I´ve seen: V_ref, 0V, last holding value, last holding value of a different channel...
And in a more realistic view:
* non linearity of switch resistance
* ringing caused by stray inductance (there may be overshot, and one microsecond later undershot..)
* ringing caused by the driving OPAMP
* moving input signal with varying dV/dt
* production tolerances
* maybe more

Klaus

Btw: nowadays we have good simualtion software. Why don´t you simulate the different conditions?

Hi,


Kindly, let me know what you think about my last reply.

Another question, when I take FFT of a S/H output, should I take my FFT samples at the end of the track phase or at the end of the hold phase? and why?

Also, should I choose my strobeperiod as my sampling period or an integer factor less than it?

 

[KlausST]

Hi,

Kindly, let me know what you think about my last reply.

According to the above condition, I would have expected that ENOB of the output signal (S/H signal) to match the ENOB of the input sinusoidal input because all included circuit elements are ideal and linear so it seems that incomplete settling of every input sample is the cause of this linearity degradation.

For reference, ENOB of an ideal sinusoidal input was about 44 bits
After S/H, ENOB becomes about 14 bits (conservative settings)

You don´t show your math ... thus we are in a guessing show.

I can only guess that your math is not correct.
It seems you just calculated the worst case error of a sample and calculated ENOB from this.
But ENOB isn´t a measure of a single sample. ENOB is a measure of a lot of samples.

In more detail:
I guess you used a sine as input, then performed the acquisition and referred this to the expected value.
Now at the TOP and BOTTOM of a sine the error will be vary small (down to zero at the horizontal parts of sine)
(given your info that the capacitor has the charge of the previous acquisition)
At zero cross you have the highest errors. But this is not an error at all. It´s basically just a tiny phase shift.
So if you compare your ideal values and the holding values ... and perform an FFT on it ... you see about no distortion, about no amplitude reduction, sine shape stays sine shape.
The only "effect" you see is the phase shift. And phase shift has no impact on ENOB at all.

Again: all this is just guessing.

Another question, when I take FFT of a S/H output, should I take my FFT samples at the end of the track phase or at the end of the hold phase? and why?

Good question.
In best case it should not matter. That´s basically the idea of a holding circuit.
Indeed what doe s "at the end of the hold phase mean"? Imortant is the time from beginning to the end of a ADConversion.
After the conversion is finished .. the hold voltage may do any crazy stuff .. it won´t matter at all.

Also, should I choose my strobeperiod as my sampling period or an integer factor less than it?

I can answer after you provided a timing diagram (sketch, hand drawn...)

Klaus