Linear regulator to reduce power supply ripple

cupoftea said:

What loads really need such power supply ripple rejection?

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What loads do you have?

If you have a low-level DC or audio signal, then power supply ripple can be a problem if it gets into the signal, depending upon the signal amplitude.
For digital signals, supply ripple typically is kept below a 100mV or so, but a higher value likely will not be a problem.

Need more info about your system to give a better answer.

Loads like analog circuits that have no common mode or PSRR rejection,
think discrete amplifiers like many circuits in a AM or FM radio from RF
down to AF. Circuits that derive bias off of a supply with passive dividers.
Discrete AF and RF oscillator circuits. Clocking circuits sensitive to jitter.....


Regards, Dana.

An old school LM317 will not offer the bandwidth to knock down switching harmonics on modern (>100kHZ) switchers. There are some I've seen that purport to have HF PSRR suited to the task.

If your ripple voltage at the (say) ADC times PSRR exceeds ADC LSB then your power supply is compromising performance.

If your ripple voltage at the (say) ADC times PSRR exceeds ADC LSB then your power supply is compromising performance.

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Thanks, i see what you mean.
In cases where the divider could tolerate having a big cap on the lower divider resistor, i assume you would say that the power supply ripple would then not matter? (within reason)

Ripple above some 10 kHz is usually rejected by LC filter rather than linear regulator.

High PSRR Voltage Regulators will serve you better than simple ones.
Analog Devices manufactures many high quality low noise and high PSRR regulators for these kind of applications.
They are also used to supply sensitive RF circuits.

You have an undefined problem with a linear solution.

Reject the task until you have measureable specs for interference and attenuation required.

Go back and verify the problem if it is CMRR noise ingress by radiation by parasitic L or C by shunting floating supplies with RF film caps. OR whether it is poor PSRR and conducted noise which is also a problem for low GBW IC's OR lack or Low ESR LV filtering OR lack of CM chokes for the BW of noise spectrum under certain connections for noise suspecibility. Demand or WRITE SPECS before doing any solution by experiment or valid data from others.

Some good answers above - the 1st step is to locate the most sensitive parts of the load ckt and work out what level of psu noise would affect them/it - a powerful and fast linear psu stage can pass thru transient current pulses to a load that requires them ( from a large storage cap ) often better than a switch mode psu can react - so this is something to bear in mind. Often, at the power levels you are talking 20V 5A, a small amount of post filtering on a switcher will allow things to work fine - just put a good amount of de-coupling on the control ckts ( e.g. a bead or 10E res followed by 470nF + 10uF ) and some quality electro-lytics near the parts that require real power ( pulses or otherwise ). Careful layout so that the most sensitive ckts are at the end of a chain of LC or RC filters works well and is used by default in RF design.

Engineering is all about being aware of the problems and defining them proactively. This takes experience.

The solutions are easy once you become aware enough to expect of all potential issues, and include them in your mental, or better ,written design specs. You then validate your assumptions in the prototype and tune as required.

We learn by failures learnt by testing to analyze and improve awareness from verification. We can simulate noise of any type, easily too. Just be aware that false noise is detected by the resonance of the 10:1 probe ground with its coax on fast risetime signals. Eliminating this measurement error is easy.