Library Characterization for SRAM

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anex16

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Hi,

I am working on designing an SRAM that would used as part of a processor. Once the schematic and layout are done, I need to create a timing library for the SRAM module. I need the liberty for further use by tools like Design Compiler, Encounter, Primetime etc.

However, I am not sure of what tool can be used for creating the timing library. I do not have access to Liberate nor am I sure if it could be of use.
I know that Encounter Library Characterizer (ELC) can be used to characterize libraries for standard cells but would it also work for bigger designs like SRAMs (say 64kB)? I do have access to ELC but I am not sure if it can be used.

I do not also have access to memory compilers and as far as I understand they are part of a technology library provided by a foundry and since I am creating my own library as well, I don't think it would be applicable to me.

Please advice as to how I should proceed. Does anyone have any experience in using ELC for this purpose?

Thanks in advance
Gaurav
 

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