[SOLVED] level shifter layout, multiple source issue

dick_freebird said:

I do not see an error report (snippet) nor markers nor the
rule's construction / intent.

I could speculate, on no basis whatsoever, that maybe a
triple nested guardring is somehow breaking the logic.
Who does that, this way?

Not knowing fill codes or anything, presuming this is basic
P-substrate JI, are both "VIN" and "VDD" rings trying to
"stamp" bulk psub? Looks kinda like, to me.

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sidun.av said:

Hi @mssong ,

First of all, you layout have a lot of fundamental mistakes. I highly recommend getting yourself familiar with CMOS device cross-sections before doing layout, because it is very important.

1. As @dick_freebird mentioned above, your triple-well structure (PSUB ring, then NWELL om the top of another NWELL) makes completely no sense. You are basically shorting the body connections of your NMOS with PMOS:


2. Your PMOS transistors have different body voltages (1.8V and 5V) -> so their NWELLs are not allowed to touch each other, because it will lead to a short between different potentials;
3. Use ERC analysis in Calibre to fix these errors (don't forget to specify power and ground potentials there).

I would recommend practice doing layout of a simple inverter first and make sure that you understand the basics.
Watch a video tutorial, i.e. this one:
Hopefully, that helps.

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