let's talk about lead compensation for load capacitance

[rambus_ddr]

lead compensation zero

When i design a three stage close loop op, I use a lead capacitor for creating a zero to canel the decreasing pole with increasing load capacitor, and get a larger bandwidth. But i found when the lead capacitor also creates a pole at three times zero, so i can not increase the bandwidth. Is it correct to use the method. May zero created bythe lead capacitor be used to cancel the op internal pole? Welcome to give your advice!

 

[Humungus]

capacitive load, resistor, compensation

First of all, be careful with the pole-zero cancelling. Actually, the frequency response improves, but you can expoilt the settling time. As pole and zero do not actually cancell, you get a "doublet". This doublet is nearly invisible in the frequency response (magnitude and phase) of your system, but it can be analyzed in the time domain. There is a good paper from Paul Gray explaining this fenomenum. Have a look to the following papers.

TITLE: Relationship between frequency response and settling time of operational amplifiers
ISSUE: IEEE Journal of Solid-State Circuits, vol. 9, pp. 347 - 352, December 1974
AUTHORS: B. Yeshwant Kamath, Robert G. Meyer, and Paul R. Gray

TITLE: Analysis of the settling behavior of an operational amplifier
ISSUE: IEEE Journal of Solid-State Circuits, vol. 17, pp. 74 - 80, February 1982
AUTHORS: C. T. Chuang

 

[rambus_ddr]

lead compensation operational

what adivce can you give for these large capacitor load and small resistor load, and three stage close loop op compensation. Thanks!

 

[mukeshk]

pole zero cancellation shd not be tried because following 2 reasons
1. variation in resistance value
2. opamp capacitive load
refer razavi's book (freq comp chapter)

If u have resistive load in ur opamp use buffer stage as a last stage.

If u hav to drive capacitive load than make sure ur stability for max possible value of cap in ur multi stage opamp. U can also use telescopic or folded architecture. here ur PM will increase with load capacitance.

 

[rambus_ddr]

Thanks for your advices!
1. the pole and zero cancellation is not required that the zero= pole, it only need the pole is less than zero, then the magnitude is decreased by 40db/dec, but the phase is not changed.so it is not reqired a accurate resistor.

2. In razavi's book about the freq comp, which is almost talked about in miller comp between the first stage and the second stage, and which created a main pole, but in our design, since there is small resistor loading and large capacitor loading, so the main pole should be the output pole. So a method must be used to cancel the pole under the unit gain freq.

 

[opamp741]

How can u say that ur system hav only fixed number of poles..There may be a pole after the zero..there may be some nondominant poles after ur zero location..

can u plz give any refrences abt ur concept..I never heard abt this concept..