Artlav
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Hello.
I'm trying to make an I2C master in an FPGA, and am getting intermittent problems with sending data.
Best fitting description is that once in a few dozen times a written byte is seen by the slave as shifted left by one bit.
I.e. it is set to read a word from 0x1754 repeatedly. Each time looks exactly the same as the previous on a scope, but once in a while it would give me a word from 0x2E54, or 0x2EA8, or 0x17A8.
I suspect there is something wrong with the timing, but i can't figure out what is it exactly, and a scope decodes it correctly every time.
That's what it looks like:
(Starts at R/W bit of slave address, then ACK, first address byte, ACK, and first pair of bits of the second byte)
Is that correct?
If not, what is wrong?
.
I'm trying to make an I2C master in an FPGA, and am getting intermittent problems with sending data.
Best fitting description is that once in a few dozen times a written byte is seen by the slave as shifted left by one bit.
I.e. it is set to read a word from 0x1754 repeatedly. Each time looks exactly the same as the previous on a scope, but once in a while it would give me a word from 0x2E54, or 0x2EA8, or 0x17A8.
I suspect there is something wrong with the timing, but i can't figure out what is it exactly, and a scope decodes it correctly every time.
That's what it looks like:
(Starts at R/W bit of slave address, then ACK, first address byte, ACK, and first pair of bits of the second byte)
Is that correct?
If not, what is wrong?
.