Led catching game in verilog

[sjhsjh]

Hi, I'm new to fpga and verilog. My problem is when I run the program, the scoreboard in a 7-segment output would increment even though I did not push any buttons. It was doing fine before I put a debouncer, but the problem is the score increments if the push button is on hold. Please help me.

Below is my code and I just used the debouncer I found online. Thank you for whoever is the owner.

module deb (clk, start, pb0, pb1, pb2, pb3, led, sc0);
	input clk, start, pb0, pb1, pb2, pb3;
	output reg [3:0] led = 16;
	output reg [6:0] sc0;
	reg [3:0] bin_sc0 = 4'b0000;
	
	reg [25:0] cnt=0;
	reg clk_1Hz;
	wire fb = led[3];
	
	debounce db0 (clk_1Hz, pb0, p0);
	debounce db1 (clk_1Hz, pb1, p1);
	debounce db2 (clk_1Hz, pb2, p2);
	debounce db3 (clk_1Hz, pb3, p3);
	
	always @(posedge clk) begin
		cnt <= cnt+1;
		
		if (cnt == 49999999) begin //if counter reaches 50M cycles
			cnt <= 0; //reset
			clk_1Hz <= 0; //low led
		end
		
		if (cnt == 24999999) begin //if counter reaches 25M cycles (1st half)
			clk_1Hz <= 1; //high led
		end
	end
	
	always @(posedge clk_1Hz) begin
		if (start == 1) begin
		
			led[0] <= fb;
			led[1] <= led[0] ^ fb;
			led[2] <= led[1] ^ fb;
			led[3] <= led[2];
			
			if ((p0 == 0 && led[0] == 1) || (p1 == 0 && led[1] == 1) || (p2 == 0 && led[2] == 1) || (p3 == 0 && led[3] == 1)) begin
				bin_sc0 <= bin_sc0+1;
			end
		end
		else if (start == 0) begin
			led <= 4'b1111;
			bin_sc0 <= 4'b0000;
		end
		
		case (bin_sc0)
			4'b0000: sc0 = 7'b1000000;
			4'b0001: sc0 = 7'b1111001;
			4'b0010: sc0 = 7'b0100100;
			4'b0011: sc0 = 7'b0110000;
			4'b0100: sc0 = 7'b0011001;
			4'b0101: sc0 = 7'b0010010;
			4'b0110: sc0 = 7'b0000010;
			4'b0111: sc0 = 7'b1111000;
			4'b1000: sc0 = 7'b0000000;
			4'b1001: sc0 = 7'b0010000;
		endcase
	end
endmodule 

module debounce(clk, pb_1, pb_out);
input clk, pb_1;
output pb_out;
wire slow_clk_en;
wire Q1,Q2,Q2_bar;
clock_enable u1(clk,pb_1,slow_clk_en);
my_dff_en d1(clk,slow_clk_en,pb_1,Q1);
my_dff_en d2(clk,slow_clk_en,Q1,Q2);
assign Q2_bar = ~Q2;
assign pb_out = Q1 & Q2_bar;
endmodule
// Slow clock enable for debouncing button 
module clock_enable(input Clk_100M,pb_1, output slow_clk_en);
    reg [26:0]counter=0;
    always @(posedge Clk_100M, negedge pb_1)
    begin
     if(pb_1==0)
              counter <= 0;
            else
       counter <= (counter>=249999)?0:counter+1;
    end
    assign slow_clk_en = (counter == 249999)?1'b1:1'b0;
endmodule
// D-flip-flop with clock enable signal for debouncing module 
module my_dff_en(input DFF_CLOCK, clock_enable,D, output reg Q=0);
    always @ (posedge DFF_CLOCK) begin
  if(clock_enable==1) 
           Q <= D;
    end
endmodule

 

[KlausST]

Hi,

did you use the simulator to verify the debouncer?
Did you use the simulator at all?

This is what I´d try first.

Klaus

 

[sjhsjh]

Are you referring to RTL simulation? I wasn't able to use it because I don't know how to write a testbench code. I just relied on the results of the FPGA itself.

 

[dpaul]

Are you referring to RTL simulation? I wasn't able to use it because I don't know how to write a testbench code.

:shock::???:

I just relied on the results of the FPGA itself.

It is a useless and wrong method to proceed. You MUST check your design using a test-bench first before moving on to implementation on FPGA board.