Preparation:
-- Record the abort points and find the corresponding lines of RTL code.
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Tips ...when advanced LEC features NOT available
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1) If abort at multiplier, then
- 1.a) observe the gate-level netlist to find out the architecture of multiplier used by the synthesizer. Then provide the information to the LEC.
OR
- 1.b) specify the architecture in the RTL code, then you can predict the architecture of resulted multiplier. And also pass the information to LEC.
2) If abort at case() statement which contains "x", then modify the RTL code.
3) If the case() statement is very large, then try to modify it.
4) If not above case, then try to partition part of the RTL code, i.e. drag some internal signal to the module's output port, then this signal can be preserved.
(note: This may impact the quality of optimization.)
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5) If all of above do not work, then try to verify the abort point by simulation. Prepare a testbench to "exhaustively" check this point and compare the RTL- and gate-level simulation result.
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