shaiko
Advanced Member level 5
- Joined
- Aug 20, 2011
- Messages
- 2,644
- Helped
- 303
- Reputation
- 608
- Reaction score
- 297
- Trophy points
- 1,363
- Activity points
- 18,302
Hello,
When instantiating a VHDL component, sometimes Modelsim doesn't allow to leave output ports OPEN while in other cases it does allow that.
What is the rule according to the LRM ?
When is it allowed to leave a component output port OPEN?
When instantiating a VHDL component, sometimes Modelsim doesn't allow to leave output ports OPEN while in other cases it does allow that.
What is the rule according to the LRM ?
When is it allowed to leave a component output port OPEN?