aramis
Member level 3
I encounter a serious problem that when i run Ncverilog with my code at normal(nondebug) mode everything is ok, but when i use linedebug mode(want to dump some wave), my code just fails.
How it can be?? is it cadence bug? and my code works well when using Modelsim5.7
My college also counter such problem, his code runs well in modelsim (have try 5.5 ~5.7 veriosn), but it fails in cadnece ncverilog normal mode at certain point. ( I try Ncverilog 2.2, 3.0, 3.1, 4.0 and LDV5.0 , they all fails at the same point)
Who has the sign off Quality?? modelsim or Cadence??
I should believe whom??
My code is
..................
always @( sel_DMA_or_fastme_currram or src_datai or
me_mc_curr_datai or me_mc_curr_datai_low or me_mc_curr_datai_high
or src_write_addr or src_write_addr or mc_write_fastme_idx or
me_mc_write_en)
begin
if(sel_DMA_or_fastme_currram == 1) // select input from DMA
begin
mbbuf_datai = src_datai;
mbuf_src_write_addr = src_write_addr;
mbuf_write_en = src_write_en; <=== This line *
end
else // select input from FastME CurrRAM
begin
if(mc_write_fastme_idx[0] == 1'b1)
begin
mbbuf_datai = me_mc_curr_datai_low;
end
else
begin
mbbuf_datai = me_mc_curr_datai_high;
end
mbuf_src_write_addr = mc_write_fastme_idx;
mbuf_write_en = me_mc_write_en; <=====This line *
end
end
mb_buffer src_mb(clk, mubbuf_src_sel_bank_w, src_read_addr, src_datao, mbuf_src_write_addr, mbuf_write_en, mbbuf_datai);
^^^^^^^^^^ mbuf_write_en
................................................
The Above code fails, becuase i see the wave dump and
"mbuf_write_en" is delayed one cycle than
"me_mc_write_en/src_write_en" signals --------->cause my code fails
If i take src_write_en/mbuf_write_en/ me_mc_write_en outside
and write another always combination logic, then it SUCCESS
always @(me_mc_write_en or sel_DMA_or_fastme_currram or src_write_en )
begin
if(sel_DMA_or_fastme_currram == 1) // select input from DMA
mbuf_write_en = src_write_en;
else
mbuf_write_en = me_mc_write_en;
end
-----------------
Why the signal "mbuf_write_en" is delayed one clk, when using first write style??
aramis
How it can be?? is it cadence bug? and my code works well when using Modelsim5.7
My college also counter such problem, his code runs well in modelsim (have try 5.5 ~5.7 veriosn), but it fails in cadnece ncverilog normal mode at certain point. ( I try Ncverilog 2.2, 3.0, 3.1, 4.0 and LDV5.0 , they all fails at the same point)
Who has the sign off Quality?? modelsim or Cadence??
I should believe whom??
My code is
..................
always @( sel_DMA_or_fastme_currram or src_datai or
me_mc_curr_datai or me_mc_curr_datai_low or me_mc_curr_datai_high
or src_write_addr or src_write_addr or mc_write_fastme_idx or
me_mc_write_en)
begin
if(sel_DMA_or_fastme_currram == 1) // select input from DMA
begin
mbbuf_datai = src_datai;
mbuf_src_write_addr = src_write_addr;
mbuf_write_en = src_write_en; <=== This line *
end
else // select input from FastME CurrRAM
begin
if(mc_write_fastme_idx[0] == 1'b1)
begin
mbbuf_datai = me_mc_curr_datai_low;
end
else
begin
mbbuf_datai = me_mc_curr_datai_high;
end
mbuf_src_write_addr = mc_write_fastme_idx;
mbuf_write_en = me_mc_write_en; <=====This line *
end
end
mb_buffer src_mb(clk, mubbuf_src_sel_bank_w, src_read_addr, src_datao, mbuf_src_write_addr, mbuf_write_en, mbbuf_datai);
^^^^^^^^^^ mbuf_write_en
................................................
The Above code fails, becuase i see the wave dump and
"mbuf_write_en" is delayed one cycle than
"me_mc_write_en/src_write_en" signals --------->cause my code fails
If i take src_write_en/mbuf_write_en/ me_mc_write_en outside
and write another always combination logic, then it SUCCESS
always @(me_mc_write_en or sel_DMA_or_fastme_currram or src_write_en )
begin
if(sel_DMA_or_fastme_currram == 1) // select input from DMA
mbuf_write_en = src_write_en;
else
mbuf_write_en = me_mc_write_en;
end
-----------------
Why the signal "mbuf_write_en" is delayed one clk, when using first write style??
aramis
