LDPC decoder project of Open cores in verilog

[sougata_vlsi13]

I am currently trying to understand the open cores project of LDPC decoder.....but there are no supportive documents available...can anyone please help me about the implementation...

 

[mrflibble]

Abandon all hope now. After that abandon opencores. You will feel better about your time-saving decision in the morning.

Because on opencores there are no supportive documents available ... ever.

PS: For other readers that may like opencores ... if you happen to know about a well documented verilog project on opencores (any design type, doesn't matter) please provide the link. In fact, pick the best documented project you have ever encountered on opencores. Hell, vhdl is fine too. I want to like the opencores concept, but up to now it's crap.

 

[Mina Magdy]

could you tell me what is the type of LDPC decoder,was it for fully parallel , partially parallel or fully serial.
if it was partially parallel it will be very difficult to understand the code even with documentation.
for fully parallel and fully serial i think if the design is for small H-matrix (small LDPC code) it will be easy and if you want any help i will try,
but first you should know from the discreption the type of that LDPC Decoder and the design H-matrix.

 

[sougata_vlsi13]

Sorry for late reply...actually i am not getting about the type of decoder concerned with partially parallel or fully serial.I have to implement the LDPC decoder with the help of belief propagation algorithm.In that process i have been provided with a H matrix,code word like [0 0 1 0 1 1] for a 4*6 matrix.The received word is r=[1 0 1 0 1 1] with a cross over probability of p=0.2.

Now the steps which i have to follow for computation is as follows:-

1.in the first step using logp/1-p i have to find out the received word and it comes like
r=[-1.3863,1.3863,-1.3863,1.3863,-1.3863,1.3863]

2.Since it is a 4*6 matrix
M11=r1=-1.3863 and M31=r1=-1.3863
for i=2,M12=r2=1.3863 and M22=r2=1.3863
.
.
.
.
for i=6 M36=r6=-1.3863 and M46=r6=-1.3863

3.Extrensic information.It is calculated by using formula

E11=log(1+tanh(M12/2)tanh(M14/2)/1-tanh(M12/2)tanh(M14/2))
Like that i have to calculate for eacha nd every node and finally a E matrix has been formed

4.calculation of LLR
L1=r1+E11+E31=some value
.
.
.
.
L6=some value
finally on the basis of BPSK scheme
Z=[0 0 1 0 1 1]

5.To check if Z is a valid codeword
S=Z.H transpose
if it comes like [0 0 0 0] then my code word is coreect otherwise have to go for next iteration.

Thats what i have to implement either in VHDL or Verilog.Please tell me how should i proceed.Its a total mathematical calculation

 

[sougata_vlsi13]

OKK..mine is fully parallel...now please tell me what approach should i take to design that with the help of above mentioned steps...plz help me

 

[Mina Magdy]

this file FU.v is used to calculate the Check node and Variable node update and to get the o/p

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this is the implementation of FU

 

[sougata_vlsi13]

Thank you sir for your reply....I am studying the code now...if i find any difficulty i will let you know...

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there are few doubts of mine...can you please clarify those of mine.

1.first of all you have taken A_a and B_a as input and check various conditions over there including that sign function.I am not getting actually what is the functionality over there.and also about the use of sign over there.It is for addsub function and similarly you have done for subadd function.

2.next you have written the case condition taking Log likelihood as input.and also one epsilon function over there....can you plz tell me wht its use...i m not getting it in block diagram.


3.I m not able to find out flag first bit and last bit in that block diagram and also the use of fifo and 0 pad.

Do you have any supportive documents for that available then it would be very helpful for me.

 

[Mina Magdy]

addsub and subadd are used to add and subtract binary numbers there are two ways
(1) that you deal with 2's complement so when you add or subtract it will easy
(2) the way that i add asign and didnt use 2's complement it works by comparison so if A is positive and B is positive so A+B is (A+B) without the sign and sign is +ve
if A is -ve and B is -ve so A+B is (A+B) without sign and sign is -ve
if A is +ve and B is -ve and A>B so A+B is (A-B) without sign and sign is +ve
if A is +ve and B is -ve and A<B so A+B is (B-A) without sign and sign is -ve
and so on i hope you got it (i made it at that way because i have that code before but you can make 2's complement this is the link https://en.wikipedia.org/wiki/Two's_complement)

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epsi function is a lookup table to calculate tanh-1(|X|/2)
this link contain a thesis for an LDPC DVB-S2 project i hope it helps
http://www.google.com.eg/url?sa=t&rct=j&q=MSc_thesis_draft_sept_20_2010&source=web&cd=1&cad=rja&ved=0CCkQFjAA&url=http%3A%2F%2Fecommons.usask.ca%2Fbitstream%2Fhandle%2F10388%2Fetd-09222010-114940%2FMSc_thesis_draft_sept_20_2010.pdf&ei=rywCUs3DH4PetAaFuoGAAQ&usg=AFQjCNG3sKatHhTaraFJow5wL_s-edtiWA&bvm=bv.50310824,d.Yms

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epsi function is a lookup table to calculate tanh-1(|X|/2)
this link contain a thesis for an LDPC DVB-S2 project i hope it helps
http://www.google.com.eg/url?sa=t&rct=j&q=MSc_thesis_draft_sept_20_2010&source=web&cd=1&cad=rja&ved=0CCkQFjAA&url=http%3A%2F%2Fecommons.usask.ca%2Fbitstream%2Fhandle%2F10388%2Fetd-09222010-114940%2FMSc_thesis_draft_sept_20_2010.pdf&ei=rywCUs3DH4PetAaFuoGAAQ&usg=AFQjCNG3sKatHhTaraFJow5wL_s-edtiWA&bvm=bv.50310824,d.Yms

 

[sougata_vlsi13]

Can you please provide the link once again for that epsi function u mentioned above....i copy pasted that but its not working....Thank you

 

[mrflibble]

google on "MSc_thesis_draft_sept_20_2010"

 

[sougata_vlsi13]

In the thesis report the block diagram of LDPC decoder has a state machine associated with it which is nothing but the controller.In the given code there is no state machine associated....then is it requied to write the code for fsm..please guide me

 

[mrflibble]

It's a thesis, what did you expect? It's tradition for research papers to give crap details when it comes to logic implementations. The best you can hope for is a pretty picture and a decent functional description. It's my pet peeve #3 regarding research papers.

So should you ever write a paper about a HDL design, remember your own pain at this moment and ... PROVIDE IMPLEMENTATION DETAILS! Thank you.

 

[sougata_vlsi13]

The post number 4 is my implementation details...i have to implement for parallel ie fully one.according to thesis report they iomplement the BD...i have to implement it through belief propagation in log domain which i already posted in my previous posts.....so if i follow according to that thesis report then i have to form the controller also

 

[sougata_vlsi13]

Can you please tell me how you calculate the values for epsi function.....for eg in the way i/p LLR is given and to calculate the o/p at epsi function...ie at the LUT

 

[mrflibble]

I usually use a matlab script for things like that. Do a for loop over all the input values you want in your lookup table, calcutate function (in this case your epsi thingie) and then printf() the result in some verilog code.

 

[sougata_vlsi13]

Thank u for ur reply....i got the values of LUT from the thesis.I able to understand about the epsi function LUT.But there is one doubt...can u tell me if i take for ex one input like 0.00100 as LLR input how it is getting converted into output 10.1100 as epsi output...is there any formula given for that???

 

[mrflibble]

Yes there is. The formula you are going to make as part of your work. Think about it for a bit, it's a good skill to have. Both the "thinking" and the "generating a lookup table" skills actually. I can probably make it in a few minutes, but then you don't learn anything. So I'd say try it. And if you are stuck with a bit of matlab code, post it so we can help with specific problems.

 

[sougata_vlsi13]

I think a lot about the generation of the LUT and also how the values has been outputted but i didnt came across a fixed solution.First i think it to be a 2's complement representation,then came across fixed point,Block floating point...also tried with different combination.It is given in thesis report that it is a 6 bit fixed point of 2.4.I have searched and tried to do with the sign bit also but not getting a perfect solution

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I dont know whether matlab is required or not but i was stuck with the formula since i dont know matlab at all....every time i searched it showed fixed vpoint tool box...

 

[mrflibble]

No need for a library just to convert floating point to fixed point. All you need to do is multiply your float by a scale factor and then roundupdowntruncatewhatever to the nearest integer.

my_fixed_point = floor(my_float * 2^4)

Assuming the input already was 0 <= my_float < 4

 

[sougata_vlsi13]

yes i also came across a scale factor but i have to take it in binary for ex in 2^somthing or 10^smthing.More precisely what i want to say is that if my value is 0.00011 which is LLR input how it is getting conveted into 11.0001 as epsi output.