LDO with PMOS pass transistor fails at SF corner

Either your FET is oversized, your gate drive is failing to
approach the rail close enough to turn the channel off
as far as subthreshold slope will let it, or your models
are sandbagged to the point that a passing simulation
result for on/off current ratio cannot be had (reality
being a separate thing).

When your CAD group imposes "4-sigma models" on
a process that runs to 3 sigma limits, this kind of pain
awaits you.

In the past I have had to go as far as setting up MC
analysis of all the WAT devices' tests and documenting
the iterations where transistor fails WAT, and negotiate
with the customer and the downstream product & test
management that bulls!t does not need to be acted
upon. Developed a map-out method to skip offending
(i.e. fails-WAT) iterations and present the product
capability stats for wafer-acceptance-passing processing.

You might try a lighter weight version of same to see if
you are being unduly taxed. Find the foundry acceptance
limits for a device of known geometry, set up that device
& stimulus, run your corners and see whether the FET
would pass or fail. I'm guessing VT and subSlope but you
can look at leakage floor too.

What you will do with the information then depends on
who's got your back, and how many job offers you can
get quickly.