At first, let me say that it is always a bit "problematic" to explain in detail the working principle (and the dimensioning) of a circuit designed by somebody else.
Nevertheless, here are some explanations:
The LDO consists of two parts: A regulated amplifier Ar (FET & CFA) and a control loop (error amplifier Ae).
* The amplifier Ar is composed of a FET in common source configuration with negative feedback. This feedback loop consists of a current conveyor (CCII-) with an additional load impedance. This combination can be regarded as a CFA with a pretty high output impedance.
* The control loop contains an OTA (also with a load impedance) which regulates the amplifier Ar via negative feedback.
* In summary:
We have a system with a "small" internal local loop (FET & CFA) and a "large" outer loop (Ar & OTA). It is a common method for control systems to use such a double-loop system, because the inner loop is quicker and can react with less delay upon changes.
This can also be explained as follows: Local negative feedback increases the bandwidth of the FET amplifier, thus allowing a step response with a smaller time delay (delay is always invers proportional to bandwidth).
Note on CC: High resistive Input Y , low-resistive input X, high-resistive output Z.
Two types are possible:
CCII+ : Ix and Iz both flowing into the terminal or out of the terminal (Ix=Iz)
CCII- : Ix=-Iz (as indicated by the current directions in the diagram, we have a CCII- type).
Comment: The currents of the CCII- type can be compared with BJT transistor currents Iy~Ib, Ix~Ie and Iz~Ic. Therefore, the CCII- sometimes is called "ideal" transistor or "diamond transistor".
I hope , the above explanations can help to understand the working principle of the circuit.