LDO Voltage Regulator

I want to Design an LDO with voltage 1.5 V and load current of 100 mA. I am not able to decide

1. what value of output capacitance will be good and if I will need a bypass output capacitor.

I am using input of 1.2 V. If I use ceramic type capacitor,

2. what is the ESR value. Kindly help me with capacitor value and corresponding ESR and ESL values . I am thinking of driving the Pmos as pass transistor using single stage op-amp and a source follower stage.

3. Also what value of Quiescent current will be okay?

If you can provide some reading material link for these, it would be even better.
Thankyou

Hi,

I am using input of 1.2 V

Click to expand...

Then the "1.5V" is the ouput voltage?
If so, then you can´t get this with an LDO, becaue an LDO has less ouput votage than input voltage. --> You need some kind of step up converter.

There are tons of explanations about ESL and ESR. Did you go through them? Give us the link to the one you used for further discussion.

It´s not clear to me wether you want to design your own IC or you want to build a circuit with discrete parts.

Klaus

Sorry, I actually meant I am using this .

I am using opamp and the inverting terminal is given 1.2V and opamp is driving PMOS whose source is at 1.8V. The output voltage required is 1.5V and is fed back to non inverting terminal of opamp. I hope you got this architecture. I want to know what output capacitance will be okay and ESR.

I know how ESL and ESR affect the circuit. I am not able to find actual values as I am not sure about what size of capacitance I must use and ESR will depend on size and I need help deciding the size and if I need to add bypass cap at output too.

I want to design a circuit with discrete parts.

Hi,

I want to design a circuit with discrete parts.

Click to expand...

I see no benefit in this. It´s your decision.

Circuit:
Look for a tutorial that shows a proven circuit and how to calculate the values.

BTW: All needs to be well considered: OPAMP, MOSFET, Rs and Cs.

It´s not that simple without tutorial.

You should be rather experienced without dedicated tutorial.
I recommend to use a good simulation tool.

Klaus

That circuit will likely oscillate without added compensation, due to the added loop gain from the MOSFET.
I suggest you simulate the design before you build, with a Spice simulator such as LTspice, looking at both the transient response and the AC Bode plot.

I am aware of oscillations and that it is difficult but all I want to know is good output capacitance value to start with and I will use bypass capacitance. iI will also add additional zero to improve phase margin. I have access to cadence spectre and am doing this to learn some difficult circuits as i am good with basic and have done some. can someone just give link to some good tutorial about LDO preferably video tutorial. Suggest some decent output cap and esr if you can?

Where will you find a P-channel Mosfet that works with such a low Vgs voltage? Or is the opamp powered so that it can drive the Mosfet gate to a negative voltage?
You forgot to say how much output current you want.

I have mentioned that the current is 100mA and the PMOS gate is driven by Opamp and source can be at 1.8 or higher. I don't see keeping PMOS in saturation a Problem with Vg>.8 V and VS=1.8V and Vd =1.5 V. Vth of low threshold voltage variant pMOS is around -400 mv.

Hi,

Hope this is the kind of stuff you're after, it may be a bit basic for you, not sure. Have fun reading!
View attachment Linear and Switching Voltage Regulator Fundamental Part 1 snva558 TI.pdf
View attachment Pass transistor info.rar

You should start from the load and work backward.
Until you know how the outside world will "challenge"
the circuit, you know nothing useful.

Load I, V (w/ worst case supply corners) sets the
pass FET attributes. Load dynamics and pass FET
attributes determines what the error amplifier (to
include pass FET drive buffer if any) has to be able
to source, sink, slew. Error amplifier design rolls into
reference accuracy as an offset adder, offset includes
mismatch and gain error. See?

Yeah. Actually, I was looking at various data sheets to find what value of Output and bypass capacitor and ESR to use for simulations. I didnt find anything very useful but got basic ideas how to go about the problem. Thankyou all

If you have pen and paper and a simulator I don't understand why you insist so much in being given a specific capacitor value to start with. You can just sweep reasonable values and see for yourself.

In any case, as it's been said before, you shall start from your specification back into device sizing. You mention 100mA of load current, I assume this is average DC. What type of load will you be driving? Is this a digital load with average DC of 100mA? If so, you will see very large current peaks and the output and you need to define what undershoot is allowed for your application. A simple Cdv/dt calculation would give you the answer. From there, you can calculate your ESR to achieve stability without compromising dynamic large signal response.

There are hundreds of good papers out there discussing this topic, just search in the Texas Instruments website and you'll find more than enough information.

Also, the simulator is there for a reason, it doesn't cost you a thing to play with it a bit... your electricity bill won't go any higher by running some parametric sweeps.