LDO transient, reducing the undershoot

[hdkwan]

LDO transient

Hi,

I am designing an LDO for 1A load.
Output voltage is 1.8V
I am using 10uF cap and 1ohm ESR resistor.
during transient the undershoot of the output voltage is 650mV.

Problem comes when I try to insert 20nH ESL inductor to the output cap.
The undershoot with the ESL can be as large as 1.8V (Output voltage drop to 0v !!!)

The rise time of my load is 0.1ns

Is there any clamping circuit that can respond within 0.1ns?
Or is there any method to reduce the undershoot?
Thanks

 

[dick_freebird]

LDO transient

LDOs are pretty fussy about the qualities of their output
filter capacitor. You may get better results by going to (N)
smaller caps since ESL and ESR both reduce in parallel.

You should size bulk capacitance to ride out any transient
load current step with less than the tolerable deflection,
figuring in the time it would take the control loop to re-settle.

Q=Istep*tsettle
C=Vstep*Q

But the bulk capacitance has to be supplemented by "fast"
(low ESL/ESR) capacitors as well, to ride out the edges.

 

[hdkwan]

Re: LDO transient

LDOs are pretty fussy about the qualities of their output
filter capacitor. You may get better results by going to (N)
smaller caps since ESL and ESR both reduce in parallel.

You should size bulk capacitance to ride out any transient
load current step with less than the tolerable deflection,
figuring in the time it would take the control loop to re-settle.

Q=Istep*tsettle
C=Vstep*Q

But the bulk capacitance has to be supplemented by "fast"
(low ESL/ESR) capacitors as well, to ride out the edges.

yes, i was thinking about putting the cap in parallel.
But I am using the ESR for stability, if i put the cap in parallel, then it will affect the stability.
What do you mean by bulk capacitance?

 

[jt_rf]

Hi,

20nH ESL and load varies at the pace of 0.1ns!!!! i think you need to reduce ESL by very good amount, else there would be no regulator action.

regds
JT

 

[FvM]

Your simulation setup is completely unrealistic. You would never have a load rising in 0.1 ns without additional (most likely
distributed) bypass caps. You may want to analyse a real LDO application in detail. It's also necessary to analyse
supply traces as transmission lines in the said speed range.

An ESR of 1 ohm seems at least unsuitable for high speed, in my opinion.

 

[dhasmana]

Use 5nH (max) ESL. 20nH ESL is unrealistic.