LDO Toplogy with NMOS pass device

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shico90

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Hello, I read that using NMOS pass device with NMOS mirror load for the OTA will give high PSRR at DC and it's equal to GmRoa*gmro. I'm asking how did I manage to get a gain from the NMOS transistor also I'm using it as source follower?
 

The second gm would be pretty low I expect, and make
output stage gain sub-unity. It would not be the classical
common-source gm because the output device is not
operating common-source. It would be a derived gm
like (dIs/dVgg) in the real configuration. The load resistor
degenerates that gm to varying degree and gm ends up
looking like (Vg-VT)/RL more or less in the output FET.
 

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