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ldo shut down circuit?

mssong

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What circuitry or devices should I add to make LDOs shut-down?

The simplest means I can think of is to attach a MOS to the gate input of the PASS TR to force it high, but the leakage current will cause the gate node to take a different voltage than expected.

Is there a better way?

1724351007292.png
 
What circuitry or devices should I add to make LDOs shut-down?

The simplest means I can think of is to attach a MOS to the gate input of the PASS TR to force it high, but the leakage current will cause the gate node to take a different voltage than expected.

Is there a better way?

View attachment 193248
What do you mean “take a different voltage…?
If your MOSFET pulls the gate close to the rail, leakage current will have a minimal effect. BUT, how will you drive that MOSFET’s gate?
 
One way is to contrive a memory cell of some kind. Rig it to detect excessively hi or low voltage. Thus causing it to change state. Apply its output (through a resistor, diode, capacitor, etc) to some vital component so that a change of state shuts down operation.

The memory effect maintains the shut down indefinitely. Without memory the system may oscillate between working and shut-down.
 
One way is to contrive a memory cell of some kind. Rig it to detect excessively hi or low voltage. Thus causing it to change state. Apply its output (through a resistor, diode, capacitor, etc) to some vital component so that a change of state shuts down operation.

The memory effect maintains the shut down indefinitely. Without memory the system may oscillate between working and shut-down.
Maybe I missed the point, but I think the OP’s question has nothing to do with detecting voltage, memory, etc. They were asking what circuit could implement the shutdown.
 
Maybe I missed the point, but I think the OP’s question has nothing to do with detecting voltage, memory, etc. They were asking what circuit could implement the shutdown.
Yes, that's right, you need an additional circuit just for the shutdown of the LDO.

If you design the circuit as shown below, the GATE NODE of PASS TR will be held close to HIGH even though OFF is HIGH.

So I thought this might be due to leakage current.

1724398744366.png

--- Updated ---

One way is to contrive a memory cell of some kind. Rig it to detect excessively hi or low voltage. Thus causing it to change state. Apply its output (through a resistor, diode, capacitor, etc) to some vital component so that a change of state shuts down operation.

The memory effect maintains the shut down indefinitely. Without memory the system may oscillate between working and shut-down.
Thanks, but I've never studied anything about memory, so I don't know what you're talking about. Could you explain it a bit more easily?
 
Hi @mssong

I am quite unsure that your gate leakage may be that significant... I should be in the order of tens-hundreds of nA, not more.
My guess would be that you probably not disabling your opamp properly and that's why you don't get what you expect. Make sure that all the gates of NMOS in your opamp are pulled low and all PMOS are pulled high, then try to pull the pass transistors' gate high and it should work.
--- Updated ---

If you design the circuit as shown below, the GATE NODE of PASS TR will be held close to HIGH even though OFF is HIGH.
This is very confusing. What is the problem here exactly? The pass transistor gate (M22) cannot be pulled high to turn it off, or the opposite - M44 hold the gate of the pass transistor high even when it is open?
In any case, I believe that proper disabling of your opamp together with pass transistors' gate pull up should do the job.
 
Last edited:

    mssong

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Hi,

whatis the purpost of the shut down?
* just to switch OFF the output?
* or reducing the total power consumption to a minimum? --> then you should shut down the OP, too.

Klaus
 

    mssong

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Hi @mssong

I am quite unsure that your gate leakage may be that significant... I should be in the order of tens-hundreds of nA, not more.
My guess would be that you probably not disabling your opamp properly and that's why you don't get what you expect. Make sure that all the gates of NMOS in your opamp are pulled low and all PMOS are pulled high, then try to pull the pass transistors' gate high and it should work.
--- Updated ---


This is very confusing. What is the problem here exactly? The pass transistor gate (M22) cannot be pulled high to turn it off, or the opposite - M44 hold the gate of the pass transistor high even when it is open?
In any case, I believe that proper disabling of your opamp together with pass transistors' gate pull up should do the job.
Hi,

whatis the purpost of the shut down?
* just to switch OFF the output?
* or reducing the total power consumption to a minimum? --> then you should shut down the OP, too.

Klaus
This is just to turn off the output.
 
This is just to turn off the output.
If you don't want to turn off the opamp, you can add one more switch disconnecting the output of the opamp from the pass transistor gate simultaneously when pulling the gate of the pass transistor high. But I don't think this is a good approach.
 

    mssong

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This is just to turn off the output.
If possible I´d keep the OPAMP in regulation (instead of saturation).
This could improve ON/OFF behaviour reagrding overshot, ringing and settling time.

Klaus
 

    mssong

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Just realized; your circuit is a terrible idea. If you pull the gate high with M44, the opamp is going to drive low, attempting to maintain regulation. POOF!!
 
Jam the pass FET gate off, cut error amp power (because
you will have a standby current spec, will you not?), and
pull any soft-start / inrush limiter to its lowest value position.
Switches cost nothing, kill 'em all.
 
Jam the pass FET gate off, cut error amp power (because
you will have a standby current spec, will you not?), and
pull any soft-start / inrush limiter to its lowest value position.
Switches cost nothing, kill 'em all.
Switches cost nothing? Please send me 100000 of those free switches that you have.
 

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