LDO PSRR with square wave

[gabrielg]

Hi all!!!
I'm designing an LDO with this characteristics:
-Vin: square wave with Vhigh=4.8V / Vlow=4.2V / thigh=tlow=4us (this comes from a rectifier, the ASIC is a passive device. Vin can go up to 6V in some case. But this is not a dynamic variation)
-Vout=3.3V
-Max Iload=700uA

If the input was some kind of DC wave, this would be an pice of cake design, but it's not due to the high frequency variations at the input.
I'm using the classic LDO structure with a PMOS as a pass transistor, and an Error Amplifier with a resistive feedback net comparing with a voltage reference.

Anyone with an idea of how to avoid the input going to the output through the source of the pass transistor?

All the best!
G.

 

[Teddy]

try replacing P with Nmos - it might improve a bit.

 

[dick_freebird]

It's not so much the thigh/tlow, but the rise/fall time that is your problem.
You need a very high dynamic PSRR meaning a high bandwidth loop with
significant remaining gain at 100kHz. There are LDOs out there with 40dB
PSRR at 1MHz, this would give you 6mV ripple if you can stabilize the loop.

That's a small load current (max) and so you ought to be able to afford
the gate drive / error amp bias current needed to hold off the input ripple.
Unless you expected a free lunch.

If you wanted to get really crazy and have an expectation that the input
will always be this particular way, you might look at compensating type
methods - regulate to DC average with an inverted image of the AC
component fighting the blow-through. But this could get messy. You
might play with feeding AC coupled input to the feedback node with
an appropriately scaled series resistor. But again, may be messy in the
sense of gain variation etc. I think what's wanted is a sporty error amp
and as small as practical pass FET.