LDO phase margin?

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mssong

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Hi, I'm designing an LDO and will be using the output as VDD for digital logic.

In this case, the output current will flow a large current of mA for a short period of time and then no current at all for the remaining long period of time. I was wondering if I should adjust the phase margin of the LDO to match the current flow of a few mA, even though there are many times when no current is flowing.
 

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Be prepared for phase margin to vary widely / wildly with load and headroom. You might even toggle between two worst cases in a pulsed load application.

Topoligic choices bear heavily on this and simple ones can be most difficult to bring into line, "across all". Collect and read papers & app notes.
 

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Low ESL means to reduce path Length/width ratio is also most important in layouts.


- lowering ESR*C is done by paralleling caps.

For production tolerances, the most difficult designs arise from high tolerances like 1 to 35 mV load regulation on 1A means 1 to 35 mohm which affects load error and BW.
of load
 
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It's also important to take into account the parasitic inductance of the bondwires to the output cap. You can assume 1nH/mm as a rule of thumb.
 

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