LDO phase margin?

[mssong]

Hi, I'm designing an LDO and will be using the output as VDD for digital logic.

In this case, the output current will flow a large current of mA for a short period of time and then no current at all for the remaining long period of time. I was wondering if I should adjust the phase margin of the LDO to match the current flow of a few mA, even though there are many times when no current is flowing.

 

[D.A.(Tony)Stewart]

Phase margin must be adequate in all load states.

This totally dependent on the ESR and ESR*C=Tau range for input and output load caps.

 

[dick_freebird]

Be prepared for phase margin to vary widely / wildly with load and headroom. You might even toggle between two worst cases in a pulsed load application.

Topoligic choices bear heavily on this and simple ones can be most difficult to bring into line, "across all". Collect and read papers & app notes.

 

[D.A.(Tony)Stewart]

http://www.seas.ucla.edu/brweb/papers/Journals/BR_Magzine5.pdf

 

[danadakk]

Min ESR output C considerations :

https://www.ti.com/lit/an/snva167a/snva167a.pdf

https://www.ti.com/lit/pdf/sszt654

https://www.analog.com/media/en/Other/Miscellaneous/PM_ldo_design_08451b.pdf

Regards, Dana.

 

[D.A.(Tony)Stewart]

Low ESL means to reduce path Length/width ratio is also most important in layouts.

- lowering ESR*C is done by paralleling caps.

For production tolerances, the most difficult designs arise from high tolerances like 1 to 35 mV load regulation on 1A means 1 to 35 mohm which affects load error and BW.

of load

 

[sidun.av]

It's also important to take into account the parasitic inductance of the bondwires to the output cap. You can assume 1nH/mm as a rule of thumb.