LDO (Low drop out regulator )

[mady79]

h_spice

I have designed a bandgap reference (1.2V) and would like to generate five voltages (<1V)using LDO .

1)How many voltages can be generated using an LDO with resistor ladder .
2)What's the typical gain and gain bandwidth of the Error Amplifier with 2pF load .
3)How does one calculate the value of the Tatalum capacitor placed in series with the ESR value & bypass capacitor .

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[mallikarjun]

ldo low drop

Dear mady79,

You can generate as many as voltages. but you have to make sure that your regulator is in stable.
How much is your load variation, supply voltage, and output voltages. Everything is decided by your load varition and again output capacitor value is also decided by the load varition and the acuuracy of the your regulator. What is the accuracy you are looking for with worst case load variation?

 

[andy2000a]

dropout regulator

Hi
How about your LDO speci ??

I ever design a LDO use bandgap + OPA buffer and
driver "large Pmos " , becuase Pmos is large and R_on samll
V_drop < 1v .. but this chip current < 1A

 

[mady79]

how do we calculate ldo regulator loss

Reference Voltage is 1.25V .I would like to generate Vref1,Vref2,Vref3 ,Vref4 reference Voltages less than 1.25V with Error AMP and feedback resistor ladder network .

This voltages are connected to a 5puf load through a switch (Clock >100MHZ ) .I would like to calculate the output Capacitor with ESR & Bypass capacitor connected to Vref1,Vref2,Vref3 & Vref4 keeping in view of stability issues .

 

[mallikarjun]

ldo low

What is your max load current? and its worst case variation.

 

[mady79]

lowdrop

Maximum load current is +/-2mA

 

[mallikarjun]

ldo calculate output capacitance

Hi,

Load current is not too much and also variation much less. You need not have to use bypass capacitor and big external capacitor with ESR. those are really expensive. probably you can try for internal compensation. what is your load switching speed? What you mean be +/-2mA ? you mean to say 1mA to 4mA. You can assure the stability by placing your parasitic pole 1/CparRoa above the UGB of your regulator.
Where Cpar - parasitic capacitance at the input of pass transistor, and Roa - amplifier output impedence. Your dominant pole would be decided by load current( i mean say impedence looking into pass transistor) and output capacitor. This pole is moving pole( If your load variation is too lary probably you could face some problem, at low load(no load) condition your regulator margin could be very less, this will push your dominent pole to higher frequency).

 

[xwcwc1234]

ldo low frequency pole

How to simualte the regulator stability with Hspice?

 

[jluhzw]

ldo(low drop-out) 레귤레이터란

How to simualte the regulator stability with Hspice?

Firstly, you can simulate loop with the H_SPICE to see there is enough PM

then, you can test its stable by the transient load step from light load current to

heavy load current or from heavy load to light load.