BlueSkyPrairie
Newbie level 4
ldo without capacitor
I am new to LDO designs, just did some reading up. Not clear about the practical choices of LDO with or without using external bypass capacitor.
A) Without external bypass capacitor, internal dominant pole
Pros: cost saving of the external bypass capacitor
Cons: 1) Need internal compensation; could use DFC (Damping Factor Control) to widen the frequency response, use dynamic bias current and/or pole-zero tracking of pass transistor output current to optimize the frequency response and stability.
2) What if the user adds in additional capacitor trying to improve noise/ripple ?
Or user may not knowing do that because the chip Vdd supply connecting to the LDO output may have Vdd-Gnd big internal on-chip bypass capacitor.
B) With external bypass capacitor
With external bypass capacitor using capacitor ESR as zero, this still becomes the earlier case A, and have the same cons without the pros.
I am more thinking of the case of external bypass capacitor as dominant pole.
Pros: 1) As long as sufficient capacitor is used, it is stable. User add additional capacitor improves noise/ripple and does not cause stability problem, though may slow down transient response.
2) Dynamic bias current and/or pole-zero tracking can still be used to optimize the frequency response.
Cons: cost of the external bypass capacitor
What is the practical good choice of designing LDO with or without external capacitor ?
My application for these LDOs are for highly integrated PMIC targeting for cellphones.
Welcome any insightful or practical comments. Thank you very much.
I am new to LDO designs, just did some reading up. Not clear about the practical choices of LDO with or without using external bypass capacitor.
A) Without external bypass capacitor, internal dominant pole
Pros: cost saving of the external bypass capacitor
Cons: 1) Need internal compensation; could use DFC (Damping Factor Control) to widen the frequency response, use dynamic bias current and/or pole-zero tracking of pass transistor output current to optimize the frequency response and stability.
2) What if the user adds in additional capacitor trying to improve noise/ripple ?
Or user may not knowing do that because the chip Vdd supply connecting to the LDO output may have Vdd-Gnd big internal on-chip bypass capacitor.
B) With external bypass capacitor
With external bypass capacitor using capacitor ESR as zero, this still becomes the earlier case A, and have the same cons without the pros.
I am more thinking of the case of external bypass capacitor as dominant pole.
Pros: 1) As long as sufficient capacitor is used, it is stable. User add additional capacitor improves noise/ripple and does not cause stability problem, though may slow down transient response.
2) Dynamic bias current and/or pole-zero tracking can still be used to optimize the frequency response.
Cons: cost of the external bypass capacitor
What is the practical good choice of designing LDO with or without external capacitor ?
My application for these LDOs are for highly integrated PMIC targeting for cellphones.
Welcome any insightful or practical comments. Thank you very much.