LDO design issue - no load condition

nidare · Jan 26, 2022

Hi

I am working on a LDO design that requires a rather large PMOS pass transistor due to the specified max current.

I have issues with pulling the pass transistor gate high enough at no load conditions to avoid the output voltage creeping upwards due to leakage in the pass transistor.

In certain corners the output voltage with no load increases around 3% which looks a bit scary.

My first question: Is this a common problem?

There is no feedback network as the reference voltage is equal to the output voltage but I have added a “dummy” load at the output that will always draw a certain current in an attempt to reduce this problem. By increasing this dummy current to about 1% of the max output current the output voltage starts behaving more nicely with no external load.

My second question: Is this commonly done and is wasting 1% of the max output current in a dummy load generally regarded as too high?

I guess the problem also relates to the output swing of the error amplifier stage as it can only swing up to one VDSAT from the supply rail?
To my understanding this can be maximised by making the VDSAT as small as possible (high W/L, low bias currents), also to be able to swing as low as possible to minimize pass transistor size.

My third question: Is it any topologies/tricks that can be done to pull the error amplifier output as far up as possible?

BradtheRad · Jan 27, 2022

Could a current mirror solve this problem?

MahmoudHassan · Jan 27, 2022

nidare said:
Hi

I am working on a LDO design that requires a rather large PMOS pass transistor due to the specified max current.

I have issues with pulling the pass transistor gate high enough at no load conditions to avoid the output voltage creeping upwards due to leakage in the pass transistor.

In certain corners the output voltage with no load increases around 3% which looks a bit scary.

My first question: Is this a common problem?

There is no feedback network as the reference voltage is equal to the output voltage but I have added a “dummy” load at the output that will always draw a certain current in an attempt to reduce this problem. By increasing this dummy current to about 1% of the max output current the output voltage starts behaving more nicely with no external load.

My second question: Is this commonly done and is wasting 1% of the max output current in a dummy load generally regarded as too high?

I guess the problem also relates to the output swing of the error amplifier stage as it can only swing up to one VDSAT from the supply rail?
To my understanding this can be maximised by making the VDSAT as small as possible (high W/L, low bias currents), also to be able to swing as low as possible to minimize pass transistor size.

My third question: Is it any topologies/tricks that can be done to pull the error amplifier output as far up as possible?

Hi
Regarding your first question:
First of all, there is a feedback loop even with no load as you are connecting the output back to the input directly and the feedback factor, in this case, is one. I think that you need to check the range of the input voltage (Common-mode input range) of the EA and check if still provides a good gain (or it can be better if you lower the input voltage). Given that you are designing an LDO, then the output voltage is in the range of 200mV less than the VDD.

With that said, I think you need to do stability analysis because one main challenge in designing the LDO (with PMOS pass transistor) is that it conventionally has two poles one at the gate of the pass transistor and the other one is at the output of the LDO (you can do transient analysis with a load current step and with no compensation you will be surprised with the output voltage !)

Back to the question of the 3% problem, I think that the current is so much low that the EA because of the FB (if designed correctly as negative feedback) is trying to push the gate voltage of the PMOS as high as possible. As a result, the output stage will have transistors that go out of saturation and that kills your gain!. Thus, the Loop gain at this condition will be very low and the EA has a large error between the reference voltage and the output voltage in doing the comparison.

The second question: You don't need to waste 1% of the max load current. However, you need to maintain the transistors in EA in saturation at the two extreme conditions the maximum load and minimum load.

Question 3: I am not able to help without knowing the topology of EA you are using.
You can use an extra stage at the output of the opamp to drive the PMOS (More effort should be done in this case with stability )

Best regards

KlausST · Jan 27, 2022

Hi,

nidare said:
My first question: Is this a common problem?

if you read datasheets of "ready to buy" voltage regulators you will often find the requirement for "minimum load".
So yes, it´s a well known problem.

nidare said:
Is this commonly done and is wasting 1% of the max output current

You are free to switch ON/OFF the dummy load.
You wrote about "pulling gate high" ... in this case you might switch ON the dummy load.

***
I´m confused: You siad "there is no feedback network" but you also wrote about an "error amplifier" .. which usually is a part of a feedback network.
How do I have to understand this?

Klaus

nidare · Jan 27, 2022

I´m confused: You siad "there is no feedback network" but you also wrote about an "error amplifier" .. which usually is a part of a feedback network.
How do I have to understand this?

It is a poor description from me regarding the feedback network: it is operating with unity gain and no resistor divider in the feedback network, therefore nothing will draw a significant current if there is no load.

The plan is to have a fairly standard architecture with NMOS diff pair + possible buffer stage (NMOS source follower with low enough VTH or OTA with unity gain) + PMOS pass transistor with large external cap (dominant pole at output.)

Hi
Regarding your first question:
First of all, there is a feedback loop even with no load as you are connecting the output back to the input directly and the feedback factor, in this case, is one. I think that you need to check the range of the input voltage (Common-mode input range) of the EA and check if still provides a good gain (or it can be better if you lower the input voltage). Given that you are designing an LDO, then the output voltage is in the range of 200mV less than the VDD.

With that said, I think you need to do stability analysis because one main challenge in designing the LDO (with PMOS pass transistor) is that it conventionally has two poles one at the gate of the pass transistor and the other one is at the output of the LDO (you can do transient analysis with a load current step and with no compensation you will be surprised with the output voltage !)

Back to the question of the 3% problem, I think that the current is so much low that the EA because of the FB (if designed correctly as negative feedback) is trying to push the gate voltage of the PMOS as high as possible. As a result, the output stage will have transistors that go out of saturation and that kills your gain!. Thus, the Loop gain at this condition will be very low and the EA has a large error between the reference voltage and the output voltage in doing the comparison.

The second question: You don't need to waste 1% of the max load current. However, you need to maintain the transistors in EA in saturation at the two extreme conditions the maximum load and minimum load.

Question 3: I am not able to help without knowing the topology of EA you are using.
You can use an extra stage at the output of the opamp to drive the PMOS (More effort should be done in this case with stability )

Best regards

Common-mode input range of the EA should be ok, gain from closed loop stability analysis reports a gain around 50dB with no load but I can see the output node from the NMOS diff pair being pushed close to the supply rail in DC analysis and this reduces the gain as you say. But isn't this unavoidable without adding some dummy load to the regulator output to avoid having the EA output go this high?

If I assume that I am able to keep everything stable from min to max load with/without a buffer stage after the EA, the stage that ends up driving the pass transistor gate can never go higher than VDD - VDSAT? Do you have any tips for a well suited buffer topology for maximizing output swing?

if you read datasheets of "ready to buy" voltage regulators you will often find the requirement for "minimum load".

I checked some datasheets and I can see some minimum load requirements on the order of 0.1% of max current so in my case with 1% is a bit too high I think. Maybe it comes down to a limitation in my process as the leakage might be on the high side. I will look into increasing the length slightly for the pass transistor or is this just a waste of area?

I will look into switching on the dummy load at low load currents, I need to find a reliable way to sense the current in that case.

Could a current mirror solve this problem?

In what way were you thinking? To sense the load current in some way?

dick_freebird · Jan 27, 2022

Some LDOs have a sink capability that fixes both DC and low-load stability issues. A quasi Class AB topology but likely quite asymmetric.

KlausST · Jan 27, 2022

Hi,

This is what I thought about. I wrongly wote "switch", but it should switch ON smoothly not to cause ringing.

Klaus

crutschow · Jan 27, 2022

BradtheRad said:
Could a current mirror solve this problem?

nidare said:
In what way were you thinking? To sense the load current in some way?

An NPN two-transistor current mirror can provide a small constant-current output load independent of the output voltage.
That way the current and power dissipated doesn't get so high at the maximum output voltage as a resistive load would do.
The dissipated power becomes proportional to V instead of V².

BradtheRad · Jan 28, 2022

nidare said:
In what way were you thinking? To sense the load current in some way?

I mentioned a current mirror because it's a method to sense one condition and use that to control the following section. The two sections do not interfere with each other thus reducing causes for instability.

From your description I got the impression that you have one stage doing all tasks, resulting in a problem of undesired interaction. Although you found certain ways to work around this, a current mirror is a convenient method (agreeing with post #8 from crutschow) that brings options so you can:

* modify your reference voltage / current in a stable and predictable manner

* drive a second pass transistor in case you wish to share the burden with the first transistor.

LDO design issue - no load condition

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