LDO Design Help

[nithinp]

I'm designing an LDO with SKY130PDK for Vreg=1.5, Vdd=1.8, Ilaod=1mA-10mA Vref=0.75. I used a 2 stage OTA I built earlier which provides a gain of 60dB and phase margin of 80deg but when I try LDO design , I get a regulated voltage of 1.5V but my gain is messes up like 6dB, I know I'm having problem with pole compensation. Please help

 

[aliarifat794]

You may need to increase the phase margin of your feedback loop. You can achieve this by adding compensation capacitors. You can use pole splitting to improve stability. This involves adding additional poles in the transfer function to mitigate phase shifts at higher frequencies. You can achieve this by adding compensation capacitors in parallel with the load or the output capacitor. For some more feedback, you can post your question to pcbway: https://www.pcbway.com/blog/25/How_to_choose_the_best_LDO_for_your_projects_.html

 

[nitishn5]

What you seem to be measuring is your closed loop gain. Which is this case is 2 or 20log(2)=6dB.

In your testbench for measuring the gain, you have not broken the loop.

 

[nithinp]

Can you tell how can i get that result

 

[nitishn5]

You have to run an stb analysis if you are using virtuoso/spectre

There are many resources online on how to run that.

 

[nithinp]

Im using open source Ngspice and Xschem

 

[nitishn5]

Use

how to run stability simulatios in ngspice - Google Search