LDO at NO LOAD condition

[ella1923]

Hi All,

I would like to ask few questions to those who have already experienced LDO design. These are my questions:

1. Is it always necessary to consider the 'no load condition' of the LDO? Why?

2. If yes, what is a good circuit architecture of error amplifier needed when other devices (pmos pass transistors, feedback resistors under no load condition) is already contributing a -52dB gain? other load conditions were not a problem because it only contribute within range of -3.05822dB~-4.71488dB.

3. What causes the -52dB gain under no load condition? Is it because my pmos pass transistor is too large? or too small?

4. Is it true that large pmos pass transistor is easier to shutdown than smaller size pass transistor?

Looking forward for any response.

Than you very much.
Ella

 

[dick_freebird]

1. You know the application, you tell us. But a general-use product
needs to not place unreasonable demands or extra components.
Zero is a nice round number.

2. Resistor feedback ladder ought to ensure that there is a load,
even if no external explicit load. But it may be high.

3. If you are getting the right answer for VOUT then there is
indeed gain, maybe the calculation / method is bad. AC
analysis can give you crappy results for gain / phase when
the pass FET is buried either full-on or full-off.

4. No, the opposite. But it's not like you have much of a choice,
size derives from dropout voltage @ max load @ worst corner.

 

[ella1923]

1. You know the application, you tell us. But a general-use product
needs to not place unreasonable demands or extra components.
Zero is a nice round number.

Right now,the one who requested the design has no specific application. Load current range(min.~max.) was specified but not with no load condition. That is why I wonder if it is always necessary to consider it. If we are given the required current range, say 100mA~200mA, do we automatically consider minimum as 0mA or just the 100mA?

2. Resistor feedback ladder ought to ensure that there is a load,
even if no external explicit load. But it may be high.

3. If you are getting the right answer for VOUT then there is
indeed gain, maybe the calculation / method is bad. AC
analysis can give you crappy results for gain / phase when
the pass FET is buried either full-on or full-off.

I can get the right VOUT since my pass transistor is large enough to drive the required current with different load conditions. What I did was, I simulated the pass transistor, feedback resistors, different loads: minimum,maximum & no load conditions without my error amplifier, to see how these devices affects the entire system. That's how I got the -52dB under no load condition. In this way I can have a rough estimate on the error amplifier characteristics needed but it seems -52dB is too much. Is this right way to determine how these devices behave when connected in a closed loop?:-?

4. No, the opposite. But it's not like you have much of a choice,
size derives from dropout voltage @ max load @ worst corner.

Yes, you are exactly right.