LDO AC simulation brain-teaser

[PSG]

Hi,

I'm designing an LDO, 5V in, 3.3 out (can't do linear reg because no headroom). I was trying to compensate it and after a few unfruitful trials, I comped it by bypassing the entire buffer stage and the output stage of the error amp. Now I get a beautiful AC response, but when I run a transient, I see ocillations on my output, at 16kHz for 10mA load, 29kHz for 20mA load, 42kHz for 30mA load ...etc... The AC response shows no issue at those frequencies. Attacheda re the schematics and the AC response simulation.
What am I doing wrong here?

Thanks for you help.

 

[LvW]

Hi,
................
Now I get a beautiful AC response, but when I run a transient, I see ocillations on my output, at 16kHz for 10mA load, 29kHz for 20mA load, 42kHz for 30mA load ...etc... The AC response shows no issue at those frequencies. Attacheda re the schematics and the AC response simulation.
What am I doing wrong here?
Thanks for you help.

Your interpretation of the ac response as shown is wrong.
The green magnitude curve shows normal (decreasing) behaviour - however the corresponding phase response (red curve) increases. This is impossible for a stable function and indicates INSTABILITY. It is necessary to stabilize the circuit.
Please, realize that you cannot trust the magnitude response alone!

 

[PSG]

Thanks LvW, I did not even notice that!
It's true that by looking at the green and red curves (no load simulation), the phase behavior does not correspond to the gain behavior. The first pole at 30mHz is OK for both but what appears to be a zero on the phase curve at 1kHz (phase goes up 90deg), shows up as a pole on the gain curve (gain slope goes from -20dB/dec to -40dB/dec), and then the next pole at 300kHz is again shown correctly on both curves.

So now, what's happening with my simulator? I'm using STB simulation in Cadence, I'm breaking the loop at the input of the error amplifier. Is that the wrong technique here? Am I missing something. I also tried to run a simple AC simulation (as opposed to STB) and I get the same type of curves (see attachment) up until about 10-20kHz, beyond that things go a little AWOL ... can someone explain that to me too??

Thanks.

 

[frankliner]

I think there is a zero then two poles.

Why is the loop gain so high? Can you just reduce the loop gain?

 

[LvW]

...................
The first pole at 30mHz is OK for both but what appears to be a zero on the phase curve at 1kHz (phase goes up 90deg), shows up as a pole on the gain curve
....................

So now, what's happening with my simulator? .

* I didnt check your circuit in detail, however: I dont think that there is a zero in your circuit!
* There is nothing wrong with your simulator!
* As I have mentioned before: Most probably, the open loop itself is unstable!
(Didnt you observe oscillations during transient simulations?)
*Question 1: What do you expect from an unstable circuit during time domain simulation? Saturation or oscillation ? Right !
*Question 2: What do you expect as a result of frequency domain simulation (ac reponse) if your circuit is unstable? WHAT IS YOUR ANSWER?
*Hint: It is very very important to know what roughly should be the result of a simulation. Otherwise you trust the machine blindly and believe everything (even if there are schematic entry errors or something like that).

 

[PSG]

LvW,

I'm honestly not sure if my circuit is unstable open-loop because I never even tried to simulate it open-loop, I didn't know that would help me in any way.
DC wise, it works fine.
This strange phase vs. gain behavior only shows up when I do the compensation this way: I'm trying to do a Nested Miller comp, but after placing that first cap I got such perfect results, I actually thought I added a zero ... where clearly I didn't.
I did notice oscillations (closed-loop) and that's why I started this thread, to try and understand what's happening here.

 

[LvW]

Hi PSG,

now I am confused a little.

Quote:
So now, what's happening with my simulator? I'm using STB simulation in Cadence, I'm breaking the loop at the input of the error amplifier. Is that the wrong technique here?

When you break the loop, you are going to simulate loop gain, or not ?
Up to now I was of the opinion that you have shown us loop gain responses in order to check the stability margins, did'nt you?

 

[PSG]

LvW,

I'n confused as well, I'm not sure I understand the difference between your 2 questions ???
I want to check the stability of my LDO. For that I break the loop at the input of the error amp (between the input of the error amp and the resistor divider at the LDO output). In order to do that I am simulating the open loop gain and phase shift so I can measure my phase margin.
Does that answer your questions?

The bottom line of all this though is I understand now I can't compensate my circuit the way I did, the phase behavior gave me false hopes. I need to find another way of comping it.

 

[LvW]

I was a bit confused because yesterday (21:36) you have stated just the opposite:

I'm honestly not sure if my circuit is unstable open-loop because I never even tried to simulate it open-loop, I didn't know that would help me in any way.

Anyway - my second question is not yet answered. My only concern was to tell you that - by doing an ac analysis - you are not allowed to derive stability properties from the magnitude response alone!

I am still of the opinion that the open loop is unstable (and - of course - the closed loop).

What about the question from frankliner : Why such a high dc open loop gain?
Perhaps you should try to reduce it.

 

[ashish_chauhan]

can you explain a bit on your schmatic as to which part is trying to do what...?

 

[PSG]

Sorry for the late reply and thank you all for helping.
I've started another thread on the forum to start anew (now that I realize my compensation scheme was not right), but please feel free to continue writing here.
New thread:


frankliner:
I'm trying to keep the gain above 60dB to get a reasonable accuracy on my LDO output, and after running corners (with maximum current load) I noticed the gain was dropping around that level. Now of course at no load the gain is quite high, but I don't think there is a way around that problem, is there?

ashish_chauhan:
the LDO is composed of an error amp, a buffer and an output stage with pass device and resistor divider (the rest on the right only represent the output cap+esr, and the loads)
the error amp is a 2-stage amplifier with a clamp at the output of the 1st stage to lower the gain
the buffer is pretty simple, no need to describe it I think, except there is a load current sensing circuit embedded in it (you sample a fraction of the load current and send it to a diode, and later on I use that to detect over-current situations)
the output stage has a 1000/0.5um PMOS device and a 1.7Mohm resistor divider to keep the quiescent current down
I want to use 2 to 5uF output cap to keep the voltage ripple down and I'm limited as far as internal comp caps for cost reason

LvW:
"my second question is not yet answered. My only concern was to tell you that - by doing an ac analysis - you are not allowed to derive stability properties from the magnitude response alone!"

I understand that and it was my mistake in the first place to not look at the gain curve more carefully, it would have saved everyone some time. I was jsut hoping there night be a valid reason why the simulator was giving me those results. I guess there isn't.

 

[abhishek26.dwivedi]

Hi LDO Experts,

I am very beginner of LDO simulation.I was just trying to simulate the open loop of LDO on Cadence spectre.My design specs are
input 1.8 V
output 1.6V
max current 50mA
minimum drop out 200mV
.18um tech
Whem i m simulating it for ac simulation i m not getting proper output.
More over since Imax is 50mA, W was coming as 5 mA.Is it right?
attached is my schematic