>> Now what can i do to make data stable for latching at the rising edge of 'w_temp'. <<
I suggest using a state machine.
There are complete books written about it (RTL hardware design using VHDL from Pong. P. Chu is an example).
The simplest kind of state machine, I think, is a clocked state machine that uses a simple counter.
Just keep in mind the following:
. All code inside the process use the signal levels as they were when the process was triggered.
A signal changed in the process is not 'activated' until the process ends.
Code:
signal State: std_logic_vector(3 downto 0);
process Sample(Clk)
if (reset = '1') then
State <= X"0";
lcd_data <= "ZZZZZZZZ";
w_temp <= '1';
else
if rising_edge(Clk) then
case State is
when X"0" => lcd_data <= D_ON;
w_temp <= '1';
State <= X"1";
when X"1" => lcd_data <= D_ON;
w_temp <= '0';
State <= X"2";
when X"2" => lcd_data <= D_ON;
w_temp <= '1';
State <= X"3";
when X"3" => lcd_data <= NIL;
w_temp <= '1';
State <= X"4";
when X"4" => lcd_data <= NIL;
w_temp <= '0';
State <= X"5";
when X"5" => lcd_data <= NIL;
w_temp <= '1';
State <= X"6";
when X"6" => lcd_data <= "ZZZZZZZZ";
w_temp <= '1';
State <= X"6";
when others lcd_data <= "ZZZZZZZZ";
w_temp <= '1';
State <= X"6";
end case;
end if;
end if;
end process;
Above code is just to illustrate it and is by no means 'good practice'. Typically state machines
are not implemented as a counter, but as an enumerated type (the compiler then can optimize
things and such).
In above code, when state is '0' the data D_ON is put on the bus, the write signale is not active, and the next state will be '1'.
At the next clock the state is '1' and the same data is put on the bus, but now the write signal is asserted and the next state will be '2'.
At the next clock the state is '2' and the same data is put on the bus, and the write signal is de-asserted and the next state will be '3'.
etc, etc, etc
Basically we have written a small program that is executed every clock. In every state we indicate what each signal should be.
Instead of indicating in each state what a signal should be, you can also use 'default' settings, and only indicate in each state
what the differences from the default signal should be, like in code below.
Remember that a process is not processed sequentially ....
Code:
process Sample(Clk)
if (reset = '1') then
State <= X"0";
lcd_data <= "ZZZZZZZZ";
w_temp <= '1';
else
if rising_edge(Clk) then
-- Default values
State <= State + 1;
lcd_data <= "ZZZZZZZZ";
w_temp <= '1';
case State is
when X"0" => lcd_data <= D_ON;
when X"1" => lcd_data <= D_ON;
w_temp <= '0';
when X"2" => lcd_data <= D_ON;
when X"3" => lcd_data <= NIL;
when X"4" => lcd_data <= NIL;
w_temp <= '0';
when X"5" => lcd_data <= NIL;
when X"6" => State <= X"6";
when others State <= X"6";
end case;
end if;
end if;
end process;