DoctorWho
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I'm doing a project to create a PLL to cover 2G-7G with LC VCO. The process is 40nm and inductance is 1nH.
I know the tuning range is a little wide, thus I might use a divide-by-2 circuit to cover the LB and concentrate on 3.5G-7G.
But I'm still not certain whether it's achievable to cover 3.5G-7G with one oscillator core. If not, my life is screwed. Anybody could give a hint on how to check this?
I know the tuning range is a little wide, thus I might use a divide-by-2 circuit to cover the LB and concentrate on 3.5G-7G.
But I'm still not certain whether it's achievable to cover 3.5G-7G with one oscillator core. If not, my life is screwed. Anybody could give a hint on how to check this?