[SOLVED] Layout Vs Schematic for multiple finger mosfets

Hello,
I have circuit in CADENCE, in which I use a cmos inverter with 5 finger for pmos and 4 finger for nmos. I have another PMOS in the same design with 10 fingers. When I do the LVS, it fails because it can not relate the inverter in the layout to the inverter in the schematic. and says the instance is missing in schematic.(Although the stand alone PMOS is being mapped correctly) when I check the Extracted schematic from the layout it matches the original schematic. Also the transient waveforms for the circuit are correct.

One more thing I would like to add that in the schematic extracted from layout, A transistor of say W = 10um with 10 fingers is shown as 10 parallel transistor with W = 1um each.

So my question how to tell LVS that these transistor in the layout are mapped to which ones in the schematic

You may need "permute parallel" to turn 10 parallel single
extracted fingers into one m=10. This could be a UI
option or could be in the rules deck, depending on who
set up your rules.

The problem was that the transistors (not only the parallel ones) were not being mapped to their respective device in the schematic view. Although the extracted view matched the schematic view. This was because I was using VDD as a label in the schematics and not for the power supply. And the transistor that were causing problem were connected to this label. Now I know that you should not use VDD as a label but only as a Pin. But thanks anyways...I followed your suggestion and while studying on the permute parallel thing I increased my knowledge Thanks!