Re: layout question
Dear ilter,
the following are the answers to your questions:
1.If I have two block(analog and digital), My digital block has nor gate, nand gate and inverter gate. How much width do my power (vdd and ground)? I use tsmc 0.18µm.
The width of the metal for power routing depends on how much current the gates draw. If you are working at reasonable speeds, i do not think that the metal width will be beyond 1um for each gate.
2.If I have six metals, which metal have low resistor? Metal1 or metal6
Obviously metal 6 will have the least resistance. Hence for top level routing use metal 6. But I would suggest that you use metal 5 instead. Keep metal 6 for any options.
3.How do I decide my power ring width?
The power ring width depends on the total current drawn from the chip. Usually it is about 1u thickness for a 1mA current drawn from power supplies.
4.Which material is Gurad ring? How do I draw?
Guard ring is actually diffusion(active) material. So, using the diffusion, you form rings and place as many number of contacts and then route it with the metal. The guard rings will be of p-type for the VSS connections and n-type(inside the n-well) for P-type connections.
I hope that I am clear