layout problem in CADENCE tool

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pgoyal

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Hello
My design of LNA is working fine when i am running schematic. I am naive at layout drawing in cadence tool. When i draw a transistor from tsmc library it brings out a big transistor say 40u with 8 fingers by default. I had also shorted its source (Ring) to PSUB. DRC is running fine but while extraction
error message "Figure causing multiple stamped connection"
can u please suggest the remedy
TIA
 

"Multi stamp error ' occurs when all the gnd or vdd connections are not shorted . So check all the gnd connections are shorted or not.
 

U will get this type of errors when ur P-sub strate is at different potentials.To avoid this error u need to connect all the substrate contacts to the ground properly.

regards ,
vijay
 

Hi,
Which tool you are using for LVS and Extraction. What you meant by LNA.
Thanks & Regards,
Shiva.
 

I'm having the same problem with my layout.
How to connect the substrate contacts to ground ? Don't really get it. Can elaborate?
 

crystal said:
I'm having the same problem with my layout.
How to connect the substrate contacts to ground ? Don't really get it. Can elaborate?
Click to expand...

Use an M1-P contact. Put several of these throughout the substrate to make sure it is at the same potential everywhere. Connect all of them to Vss.
 

i need ncsu library can u sen it to me

Added after 1 minutes:

or make a link here
 

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