Layout Parasitics Reduction Techniques

[ninge]

Hi All

Let Us discuss about parasitics (R L C) reduction techniques in layout...

Thanks in Advance,
Ninge

 

[ninge]

Hi All!!!

pls reply!!!

 

[yxo]

1) Minimum area of Poly (large parasitic capacitance and resistance)
2) Thick metal to reduce parasitic resistance
3) Many vias for nets crossing different metals for reduction resistance
4)Avoid metal1, metal 2 under diffusion
5) Use Kelvin connections for nets

 

[mists]

what is Kelvin connections, thanks!

 

[mark_lhm]

same question: what is Kelvin connections.
thanks a lot

 

[yxo]

I mean following connections. But it is not Kelvin Connection. I have mistaken.Sorry

 

[mark_lhm]

As the picture shows.
I think that is a way to reduce the noise.
Am I right?

 

[ninge]

Hi Guys thanks for your response...

 

[yxo]

As the picture shows.
I think that is a way to reduce the noise.
Am I right?

No. It is for equaling resistance to each transistor(resistor, capacitor, etc)

 

[Troy]

For parasitic capacitance - The process I am currently using has 3 layers of metal so I place noisey nets on metal3 and place a grounded metal3 run on each side of it. I then add a grounded metal 2 underneath it which connect to the grounded metal3 run on the sides. This creates the shield on the sides and below to prevent any cross talk to other runs on the sides or below it.

It could also be done the opposite way using metal1 for the noisey run and running ground metal1 rums on the sides and ground metal2 on top of it.

For parasitic resistance - The runs are laid out thick and uses multiple vias. During the floor planning the critical nets are taken into account to reduce the distance they have to travel.

 

[electronXwork]

For parasitic capacitance - The process I am currently using has 3 layers of metal so I place noisey nets on metal3 and place a grounded metal3 run on each side of it. I then add a grounded metal 2 underneath it which connect to the grounded metal3 run on the sides. This creates the shield on the sides and below to prevent any cross talk to other runs on the sides or below it.

Hi Troy,

i really appreciate your technique on how to reduce crosstalk by shielding, but can I ask how this method reduce parasitic capacitance because it seems to me that the parallel lines along with the signal line will produced more parasitic capacitance. Please enlightened me....

tnx

 

[protonixs]

For parasitic capacitance - The process I am currently using has 3 layers of metal so I place noisey nets on metal3 and place a grounded metal3 run on each side of it. I then add a grounded metal 2 underneath it which connect to the grounded metal3 run on the sides. This creates the shield on the sides and below to prevent any cross talk to other runs on the sides or below it.

Hi Troy,

i really appreciate your technique on how to reduce crosstalk by shielding, but can I ask how this method reduce parasitic capacitance because it seems to me that the parallel lines along with the signal line will produced more parasitic capacitance. Please enlightened me....

tnx

i think it would be better if the shields are hanging instead of connecting them to the ground. if the shields are to be connected to ground, there would be parasitic capacitance between the noisy line and ground. on the other hand, if they are hanging, ideally, there would be no parasitic cap between them because there is no voltage potential in the hanging metal.
the technique you have mentioned is only applicable if u want to isolate parasitic capacitance between that noisy line and some neighboring lines.

if you want to lessen parasitic capacitance and resistance, make your connection shorter and use narrower lines.
wide metals introduce lesser parasitic resistance but greater parasitic capacitance.
long lines introduce greater fringe capacitance and resistance.



hi electronXwork,
sorry that i was not able to reply your email because i attended a seminar.

Added after 17 minutes:

for capacitance
1. use higher metals in high speed/clock signal line
2. if possible, do not use minimum distance rule in high speed/clock signal line.
3. if possible, put dummy metals between 2 critical lines
4. avoid too much overlaps of metals.
5. route critical signal lines in N wells instead of Psub.

for resistance
1. avoid long lines
2. observe proper metal widths
3. use more contacts/vias
4. avoid too much shifting of metal layers

 

[Troy]

My example was for eliminating crosstalk between lines not minimizing capacitance to ground.

Leaving the shield floating only reduces the capacitance by about 1/2 (2 caps in series).

For minimizing capacitance for delays, like to ground, make the runs as short and thin as possible and run them on a higher layer of metal. Also watch out for runs on higher layers of metal.

 

[protonixs]

My example was for eliminating crosstalk between lines not minimizing capacitance to ground.

you are right Troy; and that is what i also emphasized in my comment.

 

[electronXwork]

As i suspected, Troy is reffering to the capacitive coupling of the noisy line to another signal line therefore creating crosstalk.

But for high speed circuits, the parallel lines connected to GND and run along the signal line will create more parasitic capacitace and therefore increasing the propagation delay.

For the issue of not connecting the shielding to GND, I have no idea how this works. I hope protonix will explain how.

 

[protonixs]

As i suspected, Troy is reffering to the capacitive coupling of the noisy line to another signal line therefore creating crosstalk.

But for high speed circuits, the parallel lines connected to GND and run along the signal line will create more parasitic capacitace and therefore increasing the propagation delay.

For the issue of not connecting the shielding to GND, I have no idea how this works. I hope protonix will explain how.

the floating metals serve as a node between two lines. therefore the parasitic capacitance will be halved because the parasitic capacitances are connected in series as already mentioned by troy.

 

[WalkmanXD]

the floating metals serve as a node between two lines. therefore the parasitic capacitance will be halved because the parasitic capacitances are connected in series as already mentioned by troy.

What about fringe capacitance with floating metal ?? How will it affect the total parasitic capacitance ??

 

[mrsoni]

1) Minimum area of Poly (large parasitic capacitance and resistance)
4)Avoid metal1, metal 2 under diffusion


can someone explain what these point 1 and 4 means?