[SOLVED] Layout of PMOS source and Cascode

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DharmaSlice

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Hi,

Normally when I look at a PMOS current mirror with cascode they are sized with different lengths. As an example the PMOS current source could be 7.5u/3u (W/L) and the cascode set at 7.5/0.35.

During layout then it requires two seperate regions for the PMOS sources and cascode region. However, if the Lengths are made the same the layout can be built up from a unit cell containing a PMOS current source + cascode cell in the middle.

My question is: What are the negatives for increasing the cascode length from 0.35u to 3u ?

Thanks!
 

Silicon area consumption. In order to keep the cascode's W/L ratio, you'd need a 64µ/3µ PMOS (8..9 7.5µm fingers).
 

erikl said:
Silicon area consumption. In order to keep the cascode's W/L ratio, you'd need a 64µ/3µ PMOS (8..9 7.5µm fingers).
Click to expand...

Why must the cascode have such a high W/L ratio with respect to the PMOS current source ?
 

Ask yourself what upside there is, in a long channel cascode
device? The axiom is, if it doesn't buy you something, then
stick with the minimum cost (area).

You would generally prefer that the source of the cascode
guard device move as little as possible, acting as a stiff
source follower. That argues for minimum L, although the
lambda / DIBL could move Vs as well. There could be a
"sweet spot" somewhere between min L and master (source)
L, and if you believed in the integrity of the models then
you could certainly check that out.
 




Yes, I suppose my thinking was better matching because the cascode could be embedded in the layout of the current sources. Results in bigger area but a little more robust for density and matching. I just wasnt 100% sure why the smaller L is a requirement, thanks for the answer.
 

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