[SOLVED] Layout of 3.3 and 5V MOS in TSMC 0.35um 2P4m tech

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shockingshockley

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Hello...

I would like to ask if there is a difference in the layout between 3.3 and 5V MOS. Is thick active layer involved here?
And if we can use 3.3 and 5V MOS devices in a single chip. Thank you!
 

shockingshockley said:
I would like to ask if there is a difference in the layout between 3.3 and 5V MOS. ... And if we can use 3.3 and 5V MOS devices in a single chip.
Click to expand...

Yes, in the same process, i.e. on the same chip. However, usually two different gate oxide thicknesses are used for 3.3 and 5V, i.e an option which needs -at least- two more masks. Moreover, the 5V MOSFETs must have larger W and L dimensions than the process' minimum.

shockingshockley said:
Is thick active layer involved here?
Click to expand...
No. Active actually isn't a layer, these are etched (and, mostly, implant-doped) holes in the field oxide, defining the transistor bulk areas - both the same field oxide openings for 3.3 and 5V transistors, but separate active areas for both types.
 
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