layout matching and routing issue

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Junus2012

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Dear friends

Kindly, I have two questions related to the layout

1. Does the routing management of the transistor connection effecting the matching ??, one has told me it effects but for me I think it does not, because the metallization is on the up-layer of the transistors and isolated with the oxide film. However I need your opinion please.

2. routing 4 transistors (A,B,C,D) in a current mirror (Current mirror with 4 branches) is not easy, so what about if we have a current mirror with more branches like 6 or 10 ??

Thank you very much
 

Hi,

1. if routing is not distributed equally on matched devices, it will effect beacuse of stress variations.

2. it will take more area .
 
Thank you very much bhuma7

still I am looking for the second part of my question
 

Yes, metallization over matched transistor pairs does affect matching properties:

**broken link removed**


There may be multiple reasons: hydrogen diffusion through the oxide and passivation of interface states under the gate; mechanical stress, etc. etc.


See also this paper, for a broader overview of transistor matching:

**broken link removed**

Max
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its common for a current mirror to have multiple taps, ie a bias block.
and for matching they should all be shared active with the same size of devices(for ratios you would use 3 As to 1 B) the sources would all be shared typically to a rail, with the drains being the tapped points. some will run a horizontal buss with tapped vias others will run a vertical bus over the devices with tapped vias, for matching just make sure equal bus spacing, dummy runs on the edges and the same number of tapped vias for each tap.
 
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