Layout interconnect minimum adjacent distance

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Junus2012

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Hello Friends,

I am facing during my amplifier layout a considerable shift in the phase margin. I have concluded by several test that it is also due to the coupling parasitic capacitor between the circuit interconnections.
Usually I run the interconnection with the minimum adjacent distance allowed by the used technology, so the resulted coupling capacitor is becoming higher

I have been advised to increase the distance between the connection, however, this will increase the layout area plus I don't have a rule of thump assumption to use it, for example if I should use the twice or triple the minimum distance and so on.

I would like to have your experience in this issue

Thank you in advance
Regards
 

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Might be stating the obvious, but the gain of your amplifier (and load capacitance) will influence the tolerable parasitic capacitance from interconnect, etc. So, I would generally wait until I've done my extraction to see if I'm within spec. Then redesign. But as mention, it varies with amplifier specification.

Pending on the architecture, I also spend some time floor-planning to rotate transistor or blocks such that I minimize interconnect to an extent as far as possible.
 
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Thank you jjx for your reply,

Regardless the other effects that influence my amplifier performance, my concern in this post is about the recommended minimum distance between metal connection, should I avoide constraining myself for the minimum distance? because working with minimum althaugh it reduces the layout area but it increases the parasatic coupling capacitors.
if I like to increase the distance I dont have general rule of thumb to be based on it

Regards
 

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Finding the critical coupling element(s) ought to inform any
layout changes. You might like to try getting the extracted
capacitances pushed back onto a schematic so they are more
readily observable / inspectable. I haven't done that, myself.
The alternative is to try and slog through the analog extracted
view selecting all pcapacitor instances and looking at the big
ones first. You can highlight nets for instance and see whether
any particularly nasty ones are found (like, running gate parallel
to drain for distance will give you Miller-amplified Cgd adder).

You might fine it easier to "hook it up loose" and then pack it
incrementally, checking for phase margin degradation along
the way; the point / feature at which it starts to degrade like
you see in the "present final" layout, probably holds clues.
 

    J

    Junus2012

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Thank you freeBird,
What is your common rule for routing the connections, so you route them with the minimum distance allowable or you keep some factor?
 

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I'll route anything I deem non-critical (supplies, slow logic)
at minimum, anything I recognize as a likely coupling /
loading concern I will route at gross spacing (like 10u) and
wait until the end to pack it down any tighter, when most of
the "other stuff" has become known (extracted and simulated).

The other side of the coin is, make critical traces shortest and
non-critical ones, arrange them wherever makes sense after
the critical core is tight.
 
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Thank you freebird, it is nice to hear from your experience,
i have never been worked with such a spaces of 10 µm, i am stuck to the minimum constraint, but looking to the number u gave, it will encourage me to change

I would like to ask you if there is some paid training where I can participate to improve myself in this art

Thank you once again

Regards
 

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I'm sure there are but all I've got is an ancient BSEE and 39 years of banging out one part after another....
 

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