layout extraction changing device

[aka_rabbi]

when i run the LVS for my circuit, the layout extractor translates the resistor layout i placed- rnwsti(2 pin) as rjnwsti(3 pin). so i can't pass LVS. anybody have any tips on how to fix this? i am pretty sure source side of things are perfectly ok.

 

[wwfeldman]

if you show the circuit and the simulations/measured results,
it will be easier to understand the question and provide help

 

[ljp2706]

Perhaps it is extracting the substrate diode connection? I’ve seen this happen with mosfets, 4 terminal devices in schematic, but layout has 5 terminals due to the parasitic diode. You may need to use a post processing script on the cdl netlist to get it to pass lvs.

 

[aka_rabbi]

ok here is some background into my problem-
the 1st pic is an LVS passed previous version(V2). 2nd pic is the layout spice for the resistor
the 3rd pic is the failed LVS version(V5). 4th pic shows the unwanted 3rd terminal for the resistor
$SUB=GND $[rjnwsti] --> what does it mean? What can i do to get rid of that?
@ljp2706 can you share some insight about using a post processing script to pass LVS i have no knowledge of that? thanks

 

[ljp2706]

I think the easiest thing to do would be to see if the pdk offers a device symbol/model that includes that third terminal in the schematic. That’s the one you’ll want to use. The reason there’s an extra terminal in layout is because some resistors are sitting in wells, and wells need to be biased to a certain potential to ensure they don’t forward bias. The extra terminal models this connection. In your case, it seems as if you have a resistor sitting in the substrate. It must be a p substrate because your resistor is biased at the lowest potential, GND.

Are there any differences between the previous and current versions of the design that might cause it to pass/fail LVS? If this is in virtuoso, you can try using the netset cdf parameter to add a “sub_inh” property equal to GND.

 

[timof]

Try not to do any post-processing, if possible, you may create more problems.
Most likely, your problem is caused by a mistake in the layout.

The devices are recognized from the layout by LVS tool (using seed and terminal device recognition layers).
There are rules for 2-terminal n-well resistor, and rules for 3-terminal resistors.
Obviously, your LVS detected 2-terminal resistors in the first case, but 3-terminal resistors in the second (wrong) case.
Try to find the layout differences, find what layer and shape changes did you do, and resolve it at the layout level.

Max

 

[aka_rabbi]

I figured it out finally. somebody had changed the rule file. Thanks guys for your suggestions.