LAyout design rule Questions

[020170]

**broken link removed**

R5 is minimum gate extension of poly over active

R17 is Minimum active contact to active edge spacing

Why I have to keep to the regulations like that?

if I do not, what happen?

thanks

 

[fragment]

During manufacturing wafer there are some superposition error between masks for
different layers. These rules are fixed such errors.

If R5 to make less specified value its possible shorts between source and drain.
For R17 may be poor contact to active area.

 

[sharas]

R5 - If you don't keep this rule, you cac get an increase in subthreshold current, because high stress of STI on the AA effects mobility of AA.
Another problem, especially in short channel transistors, is a lower L effective, due to optical problems in the manufacturing - the drawn rectangle of the poly will actually be round, and if the extension of the poly beyond AA is not long enough, you will have a shorter L in the poly that is near the AA edge.

R-17: If the enclosure of the AA around the contact is not big enough, the contact resistance will increase due to stress of the AA edge on the contact