Layout design issue of a multi branches current mirror

[Junus2012]

Dear friends,

I have a current mirror consisting of six branches as shown in the attached image. the NMOS transistor of these mirror stage are not sharing the drain nor the source (cascoded transistors of the currnet mirror). I have tried to match this mirror in the common centroied arrangement of ABCDEFFDCBA/FDCBAABCDEF but then ended of 12 metal layers above the matched array of transistors and 12 metal layer down the matched array. These metals are for connecting the corresponding drain and source terminal for each transistor in the both sides.

Because I was afraid that this kind of tantalization is not good for parasitic nor for the array area, I have decided to go for one dimensional inter-digitizing matching array ABCDEFFDCBA. I used the upper side of the array to connect the drains in the upper side (NMOS) and I used the down side to connect the sources. However, I have recently noticed that the transistor A for example have the longest drain connection then B and C and so on. Same thing as you see with the sources.

I would like to ask you please if this would affect the matching or the complexity will justify this connectivity.

I am looking forward to your kind opinion

 

[sutapanaki]

From your explanation I understand that these are cascode transistors for current mirrors. If this is so, then matching between cascode transistors is not really as critical as the matching of the real mirror transistors that are below the cascodes. That is also one of the reasons why cascode transistors are usually sized with minimum or close to minimum length. My opinion is, don't go for common-centroid placement for cascodes, it will only complicate the connections.

 

[Junus2012]

Dear Suta,

Thank you very much

Absolutely you are right, the cascode transistors are only to increase the output resistance of the mirror while the real NMOS mirror is defined by the down transistors. I am confirmed by your answer now