layout area of a circuit in Ledit and Virtuoso

Status
Not open for further replies.
E

electronics20

Full Member level 1
Joined
Apr 27, 2011
Messages
99
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Visit site
Activity points
1,888
Dear scholars
Is there any difference between a layout area of a circuit in Ledit and in Virtuoso? Consider a Latch with 12 transistors in TSMC 0.18um.
Thanks in advance
 
Last edited:

If you can assume identical foundry, implementation of rules
decks (and following of, in layout) and artisan skill, then
you can predict equality of outcome. But there are a lot of
fingers in various pies, between foundry, tools vendor, CAD
librarian and layout that could add discrepancies.

Now, if you let the tools auto-place and just pack to rules
based on different initial guesses, the tool itself might have
more influence.

But if I started from a schematic and a blank layout, and
hand placed everything according to my best guesses, the
tool selection would have no influence. The relative quality
of PDK implementation, and its cross-platform consistency,
might.
 
Many thanks for your precise details and exhaustive explanations. That's great. All right.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…