Layer used to isolate substrates in UMC 130nm process

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sree_lakshmi

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Hi All,

I'm doing a test layout in UMC 130 nm process.
An NFET substrate is connected to net "V6" where as all the other NFET's bulk is connected to SUB.
I dont even have design rule document with me.
Can any one say which is the layer to be used for isolating two substrates.

Thanks,
Sree
 

my wild guess would be psub2....this is a CAD layer.
if you need a real isolated psub, you need to have deep nwell.
 

but i dont see either psub layer or dnwell layer in the LSW.
for time being i changed the schematic connection to get lvs clean.
thank you
 

surround this FET wiht nwell or nwell guard ring..connected to power..... this will give local isolation for fet and thus seperate sub.... this will clean LVS..... no need to modify schematic....

best of luck..
 
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