layer generation in the full chip without DRC error

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hunhong

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Hello, I'm a RF circuit engineer in the fabless startup company.

I design the Wireless wifi chip using the TSMC 40nm RF fab.
I want to reduce the substrate noise coupling from PA - VCO & SoC - RF.
For that reason, I want to insert the low doping layer(NT_N @Tsmc40nm) in the full chip area.
How to insert this layer automatically avoiding Active area and DRC error.

Thank you.
 

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