Layer 6 Capacitance in Cadence in 180nm

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KingDarius6288

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Hi,

Attached is an interdigitated electrode, implemented using metal 6 layer in 180nm tech, with a capacitance value of 6fF. It should generate a 70% change in the gain of an OTA, but when I connect it to the OTA, nothing happens. It seems that the Cadence does not recognize it as a capacitance. Am I missing some layer in the electrode layout?
In other words, for the cadence to consider the capacitance of the electrode, should I add a specific layer or sth to the layout shown in the attached photo?

Thanks and happy new year.
 

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"Attached" how?

As a schematic pcapacitor? Library device from the foundry PDK?

Layout is not a "live" device. To get a Spectre device line you'd need to extract, "refine" to analog_extracted to get the pcapacitor instance, and then run from a config view that looks at the analog_extracted for the laid out C value
 

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From Virtuoso-Assura's Point of View, this is not a capacitor. It can never know this
 

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Dear dick-freebird

The layout shown in the figure is extracted and, its symbol is generated using Cadence. The symbol is attached to the OTA.
Am I missing something here?

Thanks
--- Updated ---

BigBoss said:
From Virtuoso-Assura's Point of View, this is not a capacitor. It can never know this
Click to expand...
Dear BigBoss,

Thanks, But we know that there is a parasitic capacitance there, as there is in extracted version. Is there any way to introduce this element as a capacitance to Cadence?
 

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There are two ways how MOM or MIM capacitors can be treated -

1. as intended devices (you can instantiate p-cells for these capacitors in the layout, and black-box them in parasitic extraction), in which case you will see device instances for these capacitors in instance section of the netlist.

2. as parasitics - in which case the parasitic extractor will take care of calculating the capacitance values, and creating parasitic capacitors the netlist. You won't see any device instances for these capacitors in the netlist.

Very often, the flow is misconfigured, so that capacitance can be double-counted or zero-counted.

Generate a DSPF file, look inside it, and see what's going on, in your netlist and in your flow.
 

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dick_freebird said:
What is underneath the symbol?
Click to expand...
This is how I did it:

The layout that you see in the attached image is extracted. Then from the Virtuoso window, using a "CMC Skill" tab, I go for the "Layout/extract" tab and "generate a pin only schematic". This pin-only schematic is opened in a Virtuoso schematic editing window. From this window, I use the "design" tab to "create a cellview from cellview". The created cell view is used on an OTA.

I hope this helps you to help me.

Thanks
--- Updated ---

Thanks timof,

Two questions, can I Implement a MOM or MIM cap, while using the same layer of metal? and how should I instantiate p-cells for these capacitors in layout? Could you please elaborate on this for me?

Thanks
 

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So you have no schematic view containing a capacitor,
and you may or may not have an analog_extracted
view containing a pcapacitor. You need one or the
other "switch views" to be found, to get to the lowest
level process cap or pcapacitor's spectre view that
ends up netlisted.

As I mentioned, you then need to "steer" the netlisting
down to that "bridge" cellview either by editing the
switch view and stop view lists (which act globally) or
create a config view (Hierarchy Editor) that you can
run your simulations from, with fine grained control
over each master's (or instance's) hierarchy traversal.
 
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KingDarius6288 said:
Dear BigBoss,

Thanks, But we know that there is a parasitic capacitance there, as there is in extracted version. Is there any way to introduce this element as a capacitance to Cadence?
Click to expand...
Parasitic Capacitances in Virtuoso Environment are defined in that manner ;
MoM, Junctions' Capacitances, Intrinsic-Extrinsic Caps etc. But this is a Fringe Capacitance and it cannot be recognized by Assura ( or by any other extraction tool ) to my knowledge. Because Assura's algorithm recognizes parasitic elements being as "corresponding" so the existing fringe capacitance between two or more "non-corresponding" element cannot be treated as cap.
This is what I know..
 

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MOM - yes.
MIM - no.

(MIM capacitors are formed by special thin metal layers, big plates, with small distance between them, inserted between some top metal layers).

You can instantiate p-cells for MOM caps (or MIM caps) provided by the foundry or created by you.
This is a standard process in layout design (I am not a layout engineer, so I never done this myself).

Or you can just draw the metal lines, and let extraction tool to calculate the parasitic capacitance between them. (don't forget to use a field solver, for accuracy).
 

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