Lattice CPLD timing optimization

Status
Not open for further replies.
A

arikp

Newbie level 4
Joined
Dec 25, 2008
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,325
I am trying to divide a 100Mhz input CPLD clk by 4 and take out this 25Mhz to another CPLD pin.

I need the best Jitter from a MACHXO2-256 device.

I am aware of the fact that placing my counter close to the IOs will help and adding FF on the counter's output will also help.

I need a working example how to locate the following group physically in the floorplan as close as possible together withing the CPLD :

Group contains : input clk pin , output pin , 2 counter FFs , one optional sampling FF after the final counter FF.

Thank you for any relevant verilog code.
 

Question: why did you decide that you need manual intervention? Does your timing analysis suggest that?

Thank you for any relevant verilog code.
Click to expand...
The "floor planning" isn't done in code - it's done via the vendor's software.

I need a working example how to locate the following group physically in the floorplan as close as possible together withing the CPLD.
Click to expand...
This is rarely necessary - esspecially with such trivial designs as yours. Lattice uses Synplify Pro, which is considered to be a very good synthesis tool.
 

The jitter on the 25MHz isn't going to be affected by the placement of any of the FFs in the design as the output is a FF that is clocked by the 100 MHz (assuming you aren't doing some ugly asynchronous set/reset FF design to generate the 25MHz clock from the 100MHz clock). The only thing that determines the jitter of the 25MHz output clock is the 100MHz input clock's period jitter.

Regards
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…