Latching period in a D flip flop

[shiv_emf]

Hii
for a D flipgflop, if the input is changing in latching period .... the output is ambiguous

now most of the time ... input signal given to FF is frm external circuitary ...
How shud v control input signal so tht this FAULT is avoided ...

in other words ... do v hac to consider this issue also ???

i will put it in other way ... two guys r designing two blocks

out of one block is input to another ..... now who shud take care abt LATCHING mismatch ? both the designers or .... help me out (

 

[newelltech]

Re: latching period

There should be a common clock to both modules and data transfer between modules must be agreed on in advance by both designers.

If this is not possible then the input need to be re-synchronized. Sample the input at a higher speed clock and then re-synchronize with a derivative clock at the desired rate. Since the derivative clock is in sync with the sampling clock, there will be no glitches, meta-stable states or full-clock jitter.

 

[shiv_emf]

latching period

tht ws nice explaination !!

suppose external signal arrives in LATCHING period ??

wht should v do for THIS prob?

 

[yln2k2]

Re: latching period

Hi ,


It is captured with synthesis constraints ( assumed launching on the same clk if not proper synchronization is taken care in side the module) .

if the module is taking I/P from external to the chip you specify i/p delay of the port which will ensure your module capture correctly ( not only input delay you should specify driving cell etc ...) ..

if the module is taking i/p from another module then one can do budgetting with 40:60 ... where you take 40% clk period inside module ...


Thanks & Regards
yln

 

[newelltech]

Re: latching period

suppose external signal arrives in LATCHING period ??

You will be sampling on the leading edge (for example) and latching on the falling edge. The signal into the latch will always be stable since it cannot change during this time.

 

[yln2k2]

Re: latching period

Hi ,


One should have correct delay information ( Max in worst case) or if it is a real time signal where you can't give correct delay treat the same singnal as asynchronous .


There are so many design methodologies for asynchronous signal ( edge detection and synchronization etc ....) ....


Thanks & Regards
yln