[SOLVED] Latches create in verilog code

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tayyab786

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i create 1d array in verilog code like this 

Code Verilog - [expand]
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reg[7:0]  channel[1:length-3];
integer i ;
 
initial 
 begin
  for (i = 1 ; i <= length-3 ; i = i+1)
   begin
    channel[i] = i * 10;
   end
 end


now in always blocks i am comparing some input logic like this 

Code Verilog - [expand]
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always@ (posedge clk or posedge rst )
     begin  
     if (rst)
      begin
             cts_1 = 11'bz ;
         cts_2 = 11'bz ;
         cts_3 = 11'bz ;
         cts_4 = 11'bz ;
         cts_5 = 11'bz ;
         cts_6 = 11'bz ;
         cts_7 = 11'bz ;
         cts_8 = 11'bz ;
         count = 1 ;
         count1 = 0 ;
     end  
    else
         begin
        if( user[1:3] == 3'b000 &&  count1[0]!=1 )   //Count1---only one time access only
             begin
              cts_1= {3'b000,channel[count]};
              count=count+1;
              count1[0]=1;
             end
            else
          begin         
              cts_1 = cts_1;
             end


the line "cts_1= {3'b000,channel[1]};" give latches

now question is how to remove latches. and why this line create latches
 
Last edited by a moderator:

Re: latches create in verilog code

Because you are using blocking assignments.
Use non-blocking ( <= ) assignment instead.

Also, why are you resetting all the values to z?
 

Re: latches create in verilog code

Blocking assignments in edge sensitive always block is surely bad design practice (don't consider special cases where they are intentionally used). But I don't understand how they could cause latch generation in this case.

I rather guess the posted code is somehow "like" the original code but essentially different. It would be a good idea to report the respective synthesis warning exactly, and to post complete entity code including variable definitions, so that we can compile it for test.
 
Re: latches create in verilog code

the initial block may have some issues -- I know some tools will accept this as a warning. Using integer types in an initial block can result in the synthesis ignoring this. If that is an issue, use generate and genvar.

I also don't see any latches here. My suspicion is that a different file is being used in synthesis or there is some other issue with the original post.

last, "cts_1 = cts_1;" is not needed.
 
Re: latches create in verilog code

i know that else statement is not necessary but it actually sure that not to create latches. because missing if else statement cause latches... i also initialize cts with zero but same warning show.

the complete code is
Code: 
module channel_selector(user,rst,clk,cts_1,cts_2,cts_3,cts_4,cts_5,cts_6,cts_7,cts_8);

parameter length = 11;

output reg [1:length]cts_1,cts_2,cts_3,cts_4,cts_5,cts_6,cts_7,cts_8;

input [1:(length-3)*3]user;
input clk,rst;

reg [7:0] count1 =0;
reg [7:0]  channel[length-4:0];
reg [1:length-3] count = 0;  

integer i ;
initial 
 begin
  for (i = 0 ; i <= length-4; i = i+1)
   begin
    channel[i] = i * 10;
   end
 end
 
 
   always@ (posedge clk or posedge rst )
	 begin 	 
	 if (rst)
	  begin
	    cts_1 =  0 ;
		 cts_2 = 11'bz ;
		 cts_3 = 11'bz ;
		 cts_4 = 11'bz ;
		 cts_5 = 11'bz ;
		 cts_6 = 11'bz ;
		 cts_7 = 11'bz ;
		 cts_8 = 11'bz ;
	  	 count = 0 ;
		 count1 = 0 ;
     end  
   	else
		 begin
      	if( (user[1:3] == 3'b000) && (count1[0]!=1) )   //Count1---only one time access only
			 begin
			  cts_1 = {3'b000,channel[count]};
			  count=count+1;
		 	  count1[0]=1;
			 end
			else
          begin			
			  cts_1 = cts_1;
			 end
			 if( (user[4:6] == 3'b001)  &&  (count1[1]!=1) )
			 begin
			  cts_2 = {3'b001,channel[count]};
			  count=count+1;
			  count1[1]=1;
			 end
			 else
          begin			
			  cts_2 = cts_2;
			 end
			 
			 if( user[7:9] == 3'b010    &&  count1[2]!=1  )
			 begin
			  cts_3 = {3'b010,channel[count]};
			  count=count+1;
			  count1[2]=1;
			 end
			 else
           begin			
			   cts_3 = cts_3;
			  end
			 
			 if( user[10:12] == 3'b011    &&  count1[3]!=1 )
			  begin
			  cts_4 = {3'b011,channel[count]};
			  count=count+1;
			  count1[3]=1;
			  end
			 else
           begin			
			   cts_4 = cts_4;
			  end
			 
			 if( user[13:15] == 3'b100   &&  count1[4]!=1  )
			  begin
			  cts_5 = {3'b100,channel[count]};
			  count=count+1;
			  count1[4]=1;
			  end
			 else
           begin			
			   cts_5 = cts_5;
			 end
			 
			 if( user[16:18] == 3'b101    &&  count1[5]!=1  )
			 begin
			  cts_6 = {3'b101,channel[count]};
			  count=count+1;
			  count1[5]=1;
			 end
			 else
           begin			
			   cts_6 = cts_6;
			  end
			 
			 if( user[19:21] == 3'b110    &&  count1[6]!=1 )
			 begin
			  cts_7 = {3'b110,channel[count]};
			  count=count+1;
			  count1[6]=1;
			 end
			 else
           begin			
			   cts_7 = cts_7;
			 end
			 
			 if( user[22:24] == 3'b111 &&  count1[7]!=1  )
			 begin
			  cts_8 = {3'b111,channel[count]};
			  count=count+1;
			  count1[7]=1;
			 end
			 else
           begin			
			   cts_8 = cts_8;
			  end

 		end
	
 	 end
	
endmodule

i know else statement is not necessary but it actually sure that not to create latches because missing if else statement might cause latches. I also initialize cts_1... with zero but same warning again show

the warning show is

 
Last edited by a moderator:

As previously guessed, the "complete code" doesn't create latches.

You are essentially misunderstanding compilation warnings like this

WARNING:Xst:1710 - FF/Latch <Mtridata_cts_8_10> (without init value) has a constant value of 1 in block <channel_selector>. This FF/Latch will be trimmed during the optimization process.
Click to expand...

It's a warning about removing signals that have no effect on the design output during optimization. "FF/Latch" refers to any memory element, not specifically latches.

I didn't check if the design serves a useful purpose, but there are no latches.

missing if else statement might cause latches
Click to expand...
It does in combinational always block, not in registered code.
 
Yes FVM you are right. I alright solve that problem.
 

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