Latch usage in modern ASIC design

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shaiko

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Hello,

When designing a digital ASIC - how often are latches used (instead of Flip Flops)?
Is it a common practice?
 

This is decided by the synthesizer that translates the HDL to netlist, depends on the SPEED/AREA trade off chosed by designer .

What matter is the final functionality of the netlist .

Elico
 

This is decided by the synthesizer
Click to expand...
Sure it is - it's not what I'm asking though.

My question was about the designer's intent...
When designing modern ASICs - how common is the practice of deliberately incorporating latches (and not Flip Flops) in the design ?
 

In our design center, we usually avoid to use latch except for the gated clock, and timing issue which could be fix by using a latch (to respect huge hold time by keeping the state during the high state of the clock.)
 

As far as I am aware latches are not used as part of standard design except gated clocks as rca just mentioned.
Reasons I know of:
a) DFT becomes very tough for latch based design. b) STA tools cannot determine (find it very tough) timing.
 
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