I think the distances are big enough, even for non-epi substrate (and probably larger than the DRs would require). I don't understand the mos width info above, because your schematic tells (at least) w=1.8
mm for the PMOS (if I read it correctly), which is reasonable - however not essential for your problem here.
The slow current rise IMHO doesn't really indicate a latch-up. The high current value of 170mA could indicate that one of the resistor banks (possibly together with its adjacent diodes' bank and the MOS switch) is short-circuited.
In your cross-section drawing I see a FOX distance between the MOS source and bulk terminals, i.e. they are not really adjacent. Could it be possible, that the voltage drop over the n-well resistance between the source and bulk contacts triggers the parasitic vertical pnp BJT (source (or drain) = emitter, n-well = basis, psub = collector), so that the rest of the circuit <D0
4, R1:R5, M1> is short-circuited?
If you can realize the control sequences suggested by
stefannm (above), you might perhaps find out about this possibility.
Good luck! erikl